nanometer-scale silicon and complementary metaloxide semiconductor (CMOS)3 devices within the next 10 or 15 years. Industry will fully utilize and exploit present lithography-based manufacturing processes to produce devices with nanometer dimensions. Nevertheless the production of these devices will be dependent on billion-dollar fabrication facilities.

A significant challenge for nanoscale science and technology is the development of truly revolutionary nanofabrication processes. These new processes might utilize aspects of synthesis and self-assembly to allow for the heterogeneous integration of a diversity of molecular components, nanocomponents, and micron-scale components into a new generation of three-dimensional structures, devices, and systems. Basically, these new nanofabrication processes would eliminate the need for prohibitively expensive fabrication facilities.

There exists as well a large number of special challenges in nanostructures having to do with regard to their electrical, mechanical, optical, materials, and chemical properties. A few of these challenges are described next.

One outstanding challenge was posed by Feynman:4 the use of the third dimension for electronic storage and processing of data. Current chips do use the third dimension for electrical interconnects. It is an open question, however, whether the tyranny of large systems would prevent effective use of the third dimension for layers of devices. Feynman maintained that only this use would provide plenty of room for future development. Integration in two dimensions has not made use of molecular precision and dimensions. In fact, not even the densities typical for solids can be achieved, since current technology is based on the existence of dilute (relative to the atomic densities of solids) donors and acceptors of electrons. Devices need to be found that can be based on solid-state densities. These devices will require control of pattern generation and perfection on a molecular scale.

New massively parallel schemes such as cellular automata or nanostructures integrated to perform quantum computing are ripe for exploration, including demonstrating in principle their potential functionality. The current state of the art has not demonstrated the feasibility of executing even a greatly simplified computational task. Once feasibility is determined, an assessment needs to be made of those circumstances in which the advantages of these approaches would out-weigh their disadvantages (e.g., the requirement of low temperature).

Biological systems such as ionic channels have great advantages over current transistors, such as an infinite on/off current ratio. However, all biological systems work on a time scale much shorter than the switching times of current silicon technology. A challenge is to find material systems and implementations that have the advantages of the biological materials and designs and that also operate at high speed.

All of these challenges will require the development of computational tools that permit the simulation of these devices from their atomistic structure to their connections to macroscopic components and their integration into large systems.


In complementary metal-oxide semiconductor (CMOS) technology, both N-type and P-type transistors are used to realize logic functions. Today, CMOS technology is the dominant semiconductor technology for microprocessors, memories, and application-specific integrated circuits. The main advantage of CMOS over negative-channel metal oxide semiconductor (NMOS) and bipolar technology is the much smaller power dissipation. Unlike NMOS or bipolar circuits, a CMOS circuit has almost no static power dissipation. Power is only dissipated in case the circuit actually switches. This allows integrating many more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.


Richard P. Feynman, “There’s Plenty of Room at the Bottom,” Lecture at the annual meeting of the American Physical Society, California Institute of Technology, December 29, 1959.

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