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to “captive” chip design and manufacture internal to a company. This model is most prevalent in Japan but still exists in the United States, primarily at IBM, where nearly 50 percent of chip output in 2000 was for captive use.2 Other systems companies, such as Apple Computer or Cisco, that don’t make or sell chips may nevertheless design them for internal use. These chips may or may not be counted in merchant data depending on whether they are manufactured by a branded ASIC company, such as LSI Logic (which would be counted), or by a manufacturing-services “foundry,” such as Taiwan Semiconductor Manufacturing Corporation (which wouldn’t be included). All foundry sales are excluded from this analysis to prevent double counting.

The work of engineers who design, manufacture, and market chips has been transformed by the continuous progression of manufacturing technology, which has evolved for more than 30 years along a trajectory known as “Moore’s Law,” the name given to a prediction made in a 1965 article by Gordon Moore. Moore, who co-founded Intel a few years later, predicted that the cost-minimizing number of transistors that could be manufactured on a chip would double every year (later revised to every two years). The industry has maintained this exponential pace for more than 30 years.3

Moore’s prediction was based on several factors, such as the ability to control manufacturing defects, but the driving technological force has been a steady reduction in the size of transistors. The number of transistors leading-edge producers can fabricate in a given area of silicon has doubled roughly every three years. From 1995 to 2003, the pace accelerated and the number doubled every two years.4

This relentless miniaturization is now reaching the molecular level. The smallest “linewidth” (feature on the chip surface) has shrunk from two microns in 1980 to less than one-tenth of a micron (100 nanometers [nm]) a quartercentury later. Viewed in cross-section, the thickness of horizontal layers of material deposited on the silicon surface is currently about 1.2 nm. For an idea of the scale involved, the width of a human hair is about 100 microns, and the width of a molecule is about 1 nm (one-thousandth of a micron).

This progress has involved considerable expense for R&D, and the cost of each generation of factories has steadily increased. By 2003 the price tag for a fab of minimum efficient scale was more than $3 billion.

The Moore’s Law trajectory has led to growing complexity of the industry’s most important chip designs. The size of a design team depends on the complexity of the project, the speed with which it must be completed, and the resources available. Design teams can be as small as a few engineers, and project duration can vary from months to years. A chip like Intel’s Pentium 4, with 42 million transistors fabricated on a 180 nm linewidth process, engaged hundreds of design engineers for the full length of a five-year project.5

Functional integration has reached a point at which certain chips encompass most of the individual components that populated the circuit board of earlier systems, giving rise to the name “system on a chip” (SOC). SOC integration offers the benefits of speed, power, reliability, size, and cost relative to the use of separate chips.

Although the manufacturing costs of an SOC are lower than for the separate components it replaces, the fixed costs of a complex design can be significantly higher. A major reason is that system-level integration has drawn chip companies into software development because system software should be generated in parallel with the system-level chip to ensure coherence. Chip companies also offer their customers software-development environments, and even applications, to help differentiate their chips from those of their competitors. In a large chip-development project, software can now account for half the engineering hours.

U.S. chip companies accounted for about half of the industry’s revenue in 2005, with Intel alone commanding about 15 percent of the market. The only U.S.-based firms in the 2005 global top 10 were Intel and Texas Instruments, but the United States has a great many mid-size companies that account for about half of the top 50. Some of these are “fabless” companies that design and market chips but leave the manufacturing to other companies, primarily Asian contract manufacturers known as foundries. All new entrants to the chip industry in recent years have adopted the fabless model.

Fabless revenue has grown much faster (compound annual growth rate of 20 percent) than the semiconductor industry as a whole (7 percent) over the last 10 years. In 2005, the largest fabless companies, Qualcomm, Broadcom, and Nvidia, each had revenues of more than $2 billion.

The discussion in this paper of how the labor market for semiconductor engineers, both domestic and worldwide, has been changing in response to changes in skill requirements is based on our ongoing interview-based research on the globalization of the semiconductor industry. Since the early 1990s, the Berkeley Sloan Semiconductor Program has collected data at semiconductor companies globally.6 In the past seven years the authors have interviewed managers and executives at dozens of semiconductor companies (both integrated and fabless) in the United States, Japan, Taiwan,

2

IC Insights data reported in Russ Arensman, “Big Blue Silicon,” Electronic Business, November 2001.

3

The revision occurred in 1975 (John Oates, “Moore’s Law is 40,” The Register, April 13, 2005).

4

Mark LaPedus, “ITRS chip roadmap returns to three-year cycle,” Silicon Strategies, January 21, 2004.

5

Terry Costlow, “Comms held Pentium 4 team together,” EE Times, November 1, 2000. “Linewidth” refers to the size of the features etched on a wafer during the fabrication process. Each semiconductor process generation is named for the smallest feature that can be produced.

6

The Competitive Semiconductor Manufacturing Program is a multidisciplinary study of the semiconductor industry established in 1991 by a grant from the Alfred P. Sloan Foundation with additional support from the semiconductor industry. Further details are available at esrc.berkeley.edu/csm/ and iir.berkeley.edu/worktech/.



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