for the large-scale assembly of nanostructures (Akin et al., 2007; Ruan et al., 2007).
We believe that novel routes, which would be available with self-assembly processing and highly integrated materials, could circumvent current challenges of CMOS to achieve environmental friendliness, thermal balance, dielectric quality, and manageable capital costs of next-generation fabrication facilities—if we can develop massively parallel integration of SWNTs and semiconducting, defect-tolerant nanowires.
Assembly based on biomolecular recognition is a promising approach for constructing complex architectures from molecular building blocks, such as SWNTs and NCs (Ravindran et al., 2003). In the Ozkans’ laboratories at the University of California, Riverside (UCR), researchers are using a “tiered” approach to the nanomanufacturing of molecular electronics to address several issues: gaining an understanding of charge-carrier transport across bio-inorganic interfaces; ensuring error-free repeatability of the synthesis of hybrid building blocks; and directing the integration of nanoscale components (including assembled architectures, nanowires, and nanodevices) on silicon (Si) platforms. Figure 1 shows two