Appendix C
Background Information on Radiation Hardening for Detectors

SPACE RADIATION ENVIRONMENT

All focal plane arrays suffer risk of radiation damage in the space environment. The need for radiation hardening of sensors and detectors has become crucial with the strategic goal of creating autonomous spacecraft which rely on on-board information processing. Most satellites are deployed in orbit around the earth. The lowest radiation doses occur in low Earth orbit (LEO), less than 500 km from the surface. Only a few heavy ions penetrate the magnetic fields to this level. In the Polar Regions, there are slightly increased levels due to the Van Allen belts which will allow more heavy ions to penetrate. At geosynchronous orbit, doses are somewhat higher, but still low compared to interplanetary space due to geomagnetic shielding. However, more heavy ions can penetrate to this level than for LEO. As ions penetrate the skin of the space craft, they can emit X-rays. These X-rays will enter the detector and semiconductor materials, and cause the different layers to ionize. This can be temporary, such as corrupting the contents of a memory cell, or permanent, when the ionization triggers latchup in the device. The charge injected into the device will collect at a circuit node and cause data in the device to change.

Electrons and X-rays produce electron-hole pairs which are normally collected at the power supply nodes. The ROIC and the detector respond differently to the ionization. Ionization can cause eventual shifts in MOS transistor thresholds, which causes changes in the device characteristics. When there is no bias on the transistor, almost all of the electron-hole pairs immediately recombine. When there is a



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Appendix C Background Information on Radiation Hardening for Detectors SPACE RADIATION ENVIRONMENT All focal plane arrays suffer risk of radiation damage in the space environ- ment. The need for radiation hardening of sensors and detectors has become crucial with the strategic goal of creating autonomous spacecraft which rely on on-board information processing. Most satellites are deployed in orbit around the earth. The lowest radiation doses occur in low Earth orbit (LEO), less than 500 km from the surface. Only a few heavy ions penetrate the magnetic fields to this level. In the Polar Regions, there are slightly increased levels due to the Van Allen belts which will allow more heavy ions to penetrate. At geosynchronous orbit, doses are somewhat higher, but still low compared to interplanetary space due to geomagnetic shielding. However, more heavy ions can penetrate to this level than for LEO. As ions penetrate the skin of the space craft, they can emit X-rays. These X-rays will enter the detector and semiconductor materials, and cause the differ- ent layers to ionize. This can be temporary, such as corrupting the contents of a memory cell, or permanent, when the ionization triggers latchup in the device. The charge injected into the device will collect at a circuit node and cause data in the device to change. Electrons and X-rays produce electron-hole pairs which are normally collected at the power supply nodes. The ROIC and the detector respond differently to the ionization. Ionization can cause eventual shifts in MOS transistor thresholds, which causes changes in the device characteristics. When there is no bias on the transis- tor, almost all of the electron-hole pairs immediately recombine. When there is a 

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seeing Photons  positive bias, however, the electrons are swept away while the holes migrate slowly to the negative channel, and become trapped. This causes N-channel enhancement transistors to become easier to turn on, while P-channel transistors are harder to turn on adversely impacting the ROIC performance. There are four basic categories of radiation vulnerabilities for an integrated circuit. These four effects are Neutron, Total Ionizing Dose (TID), Transient Dose, and Single Event Effect (SEE). 1. Neutron Effects: When neutrons strike a semiconductor chip, they displace atoms within the crystal lattice structure. The minority carrier lifetime is reduced because of the increased density of recombination centers. Silicon devices begin exhibiting changes in their electrical characteristics at levels of 1×1010 to 1×1011 neutrons/cm2. Because bipolar components are minority carrier type devices, neutron radiation affects them at lower doses than for MOS devices. In bipolar integrated circuits, the base transit time and width are the main physical parameters affected. Neutron radiation significantly reduces gain in bipolar devices. MOS devices aren’t normally affected until levels of 1×1015 neutrons/cm2 are reached. 2. Total Ionizing Dose Effects: Total ionizing dose is the accumulation of ion- izing radiation over time, typically measured in rads. Slow, steady accumu- lation of ionization over the life of an integrated circuit causes performance parameters to degrade. Eventually, the device fails. The total dose creates a number of electron-hole pairs in the silicon dioxide layers of MOS devices. As these recombine, they create photocurrents and changes in the threshold voltage that make n-channel devices easier to turn on and p-channel devices more difficult to turn on. Even though some recovery and self-healing takes place in the device, the change is essentially permanent. Some holes created during ionizing pulses are trapped at defect centers near the silicon/silicon oxide interface. Charges induced in the device create a field across the gate oxide sufficiently high to cause the gate oxide to fail, or sufficient carriers are generated in the gate oxide itself to cause failure. 3. Transient Dose Effects: A transient dose is a high-level pulse of radiation, typical in a nuclear burst, which generates photocurrents in all semiconduc- tor regions. This pulse creates sudden, immediate effects such as changes in logic states, corruption of a memory cell’s content, or circuit ringing. If the pulse is large enough, permanent damage may occur. Transient doses can also cause junction breakdown or trigger latch-up, destroying the device. 4. Single Event Effect (SEE): Single event effects typically only affect digital devices significantly. A SEE occurs when a single high-energy particle strikes a device, leaving behind an ionized track. The ionization along the path of the impinging particle collects at a circuit node. If the charge is high

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aPPendix c  enough, it can create a soft error single event upset (SEU), such as a bit flip, a change in state that causes a momentary glitch in the device output, or corruption of the data in a storage element. A SEE can possibly trigger a device latch-up and burnout. Latch-up occurs when sufficient current is induced in part of the device that it causes the device to latch into a fixed state regardless of circuit input. Burnout occurs when the radiation induces sufficient power dissipation to cause catastrophic device failure. Burnout often occurs as a result of latch-up. SEEs can wreak havoc on satellites, spacecraft, and aircraft as well. Therefore, circuits used in aerospace controls systems must be protected from potentially disastrous SEEs. a. Single Event Upsets (SEU): These are also known as soft errors that occur due to either the deposition of depletion of charge by a single ion at a circuit node, causing a change of state in a memory cell. In very sensitive devices, a single ion hit can also cause multiple-bit upsets (MBUs) in adjacent memory cells. This type of event causes no permanent damage and the device can be reprogrammed for correct function after such an event has occurred. b. Single Event Latch-up (SEL): This can occur in any semiconductor device which has a parasitic n-p-n-p path. A single heavy ion or high energy proton passing through either the base emitter junction of the parasitic n-p-n transistor, or the emitter-base junction of the p- n-p transistor can initiate regenerative action. This leads to excessive power supply current and loss of device functionality. The device can burnout unless the current is limited or the power to the device is reset. SEL is the most concern in bulk CMOS devices. c. Single Event Snapback: This is also a regenerative current mecha- nism similar to SEL, but a device does not need to have a p-n-p structure. It can be triggered in a n-channel MOS transistor with large currents, such as IC output driver devices, by a single event hit-induced avalanche multiplication near the drain junction of the device. d. Single Event-Induced Burnout (SEB): This event may occur in power MOSFETs when the passage of a single heavy ion forward biases the thin body region under the source of the device. If the drain-to-source voltage of the device exceeds the local breakdown voltage of the parasitic bipolar, the device can burn out due to large currents and high local power dissipation. e. Single Event Gate Rupture (SEGR): This has been observed due to heavy ion hits in power MOSFETs when a large bias is applied to the gate, leading to thermal breakdown and destruction of the gate oxide. It can also occur in nonvolatile memories such as EEPROM

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seeing Photons 0 during write or erase operations, the time when high voltage is ap- plied to the gate. During the past several decades, several companies have developed manufac- turing processes to produce a range of rad-hard electronic products. These pro- cesses are somewhat different from the ones used in commercial foundries because they include a few modified process steps that produce circuits with greater radia- tion resistance. These parts are more expensive than their commercial counterparts and have lagged several generations behind in terms of processing speed, power, and size. Moreover, many companies that were in the business of supplying rad- hard components a decade ago have dropped out of the market. Only two foundries remain active today—Honeywell and Sandia National Laboratories. The high cost of maintaining dedicated foundries to create space electronics has motivated an exploration of alternatives for next-generation space systems. One strategy in particular has been gaining popularity in recent years. Known as radiation hardening by design (RHBD), this approach relies solely on circuit design techniques to mitigate the damage, functional upsets, and data loss caused by space radiation.1 Different aspects of this approach have been in use for some time, but most frequently in combination with dedicated rad-hard manufacturing facilities. More recently, a number of research institutions and corporations have demonstrated the basic feasibility of RHBD using standard commercial foundries; however, to satisfy the military’s need for a wide range of part types and hardness levels, a self- sustaining RHBD infrastructure must be established, and the RHBD approach must be proven robust enough to use without some degree of fabrication process control.2 The manufacturing processes used to build commercial electronic components in the 1970s and 1980s were severely inadequate to meet the needs of the space community. But as commercial CMOS processes have advanced, the inherent ra- diation resistance of these devices has improved—and thus, the RHBD approach has become more feasible.3 For example, the current that flows through CMOS transistors is governed by a low-voltage gate over each device, isolated by a layer of oxide. These insulating layers can develop a charge after long exposure to ionizing radiation, and this charge can affect the flow of current through the device; but 1 D.R. Alexander,D.G. Mavis, C.P. Brothers, and J.R. Chavez, “Design Issues for Radiation Tolerant Microcircuits in Space,”  IEEE Nuclear and Space Radiation Effects Conference (NSREC) Short Course, V-1 (1996). 2 Ibid. 3 Ibid.

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aPPendix c  as circuits have shrunk, the thicknesses of these insulating layers have decreased, presenting a decreased opportunity for charge buildup. The radiation-induced increases in leakage current result in unregulated cur- rent flowing across unintended areas of the semiconductor.4,5,6 When leakage cur- rent bypasses the transistor’s isolated regions, it degrades the ability to distinguish the transistor’s “on” and “off ” states. Leakage also increases the circuit’s background current, or the amount of current flowing when the device is in a quiescent state. Such an increase, multiplied by the tens of millions of switches in each circuit, can drive up power consumption, increasing heat-dissipation needs and prematurely draining the power source of the satellite. In an extreme case, the isolation between discrete components can also be lost, rendering the circuit useless.7,8,9 There are interface areas which are prone to leakage in a radiation environment such as edges of the transistors where the thin gate oxide abuts with the much thicker field oxide. The process traditionally used to manufacture the transistor borders can induce significant material stress, which may facilitate the increase in leakage current when exposed to radiation. The newest isolation-oxide manufac- turing processes impart less stress and seem to have achieved a greater inherent radiation resistance. It has been shown that total-dose effects can be mitigated by designing transis- tors in an enclosed shape, thereby eliminating the edges that can trigger current leakage along the borders of conventional transistors. Current flows from the center to the outside of these devices, making them immune to edge leakage current, but requiring a larger area for each transistor. Furthermore, transistor-to-transistor leakage can be reduced by incorporating guard bands around individual transistors 4 Ibid. 5 G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Florian, A. Giraldo, E. Heijne, P. Jarron, K. Kloukinas, A. Marchioro, P. Moreira, and W. Snoeys, “Radiation Tolerant VLSI Circuits in Standard Deep Submicron CMOS Technologies for the LHC Experiments: Practical Design Aspects,” IEEE Transactions on Nuclear Science, Vol. 46, pp. 1690-1696 (1999). 6 T. Calin, M. Nicolaidis, and R. Valazco, “Upset Hardened Memory Design for Submicron CMOS Technology,” IEEE Transactions on Nuclear Science, Vol. 43, pp. 2874-2878 (1996). 7 D.R. Alexander, D.G. Mavis, C.P. Brothers, and J.R. Chavez, “Design Issues for Radiation Tolerant Microcircuits in Space,”  IEEE Nuclear and Space Radiation Effects Conference (NSREC) Short Course, V-1 (1996). 8 G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Florian, A. Giraldo, E. Heijne, P. Jarron, K. Kloukinas, A. Marchioro, P. Moreira, and W. Snoeys, “Radiation Tolerant VLSI Circuits in Standard Deep Submicron CMOS Technologies for the LHC Experiments: Practical Design Aspects,” IEEE Transactions on Nuclear Science, Vol. 46, pp. 1690-1696 (1999). 9 T. Calin, M. Nicolaidis, and R. Valazco, “Upset Hardened Memory Design for Submicron CMOS Technology,” IEEE Transactions on Nuclear Science, Vol. 43, pp. 2874-2878 (1996).

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seeing Photons  or groups of transistors.10 Other novel techniques are being applied to conventional transistor switches to boost their immunity to total ionizing dose radiation. These techniques consume area in the design, thereby reducing the total number of tran- sistors available for a given circuit function and increasing the capacitance, and thus the power consumption, of the circuit. The trade-off may be worthwhile: Using RHBD, several manufacturers have demonstrated radiation hardness in excess of 20 Megarads using commercial CMOS foundries, making them suitable for use in nuclear reactors as well as severe space environments.11,12 Companies such as Raytheon Vision systems, Teledyne Imaging Systems and BAE are all experienced in manufacturing RHBD products for space applications. Single-event upsets require different mitigation techniques. Single-event upsets occur when energetic particles deposit charge into memory circuits, causing stored data to change state (from a “1” to a “0,” for example). As circuits shrink and transis- tor volumes become smaller, the total charge needed to cause an upset in a circuit element decreases. Thus, even protons moving through the circuit may deposit sufficient charge to disrupt sensitive locations. Susceptibility to single-event upsets can be reduced by increasing the amount of charge needed to trigger a bit flip or by providing feedback resistors that give the circuit time to recover from a particle strike. Perhaps the most common approach is to use redundant information stor- age or error-checking circuitry. For example, a technique known as “voting logic” can be used to catch and correct potential errors in latches. With this technique, a single latch does not affect a change in bit state; rather, several identical latches are queried, and the state will only change if the majority of latches are in agreement. Thus, a single latch error will be “voted away” by the others. Another technique useful for overcoming single-event upsets is known as “er- ror detection and correction.” In this technique, the system architecture provides extra check bits in each stored word in memory; when these extra bits are read and interrogated, errors become apparent and can be corrected. Perhaps the simplest approach would be to insert a single bit that denotes whether the content of a word has an even or odd parity; this requires minimal overhead, but does not automati- cally identify the location of any observed errors. On the other hand, to uniquely 10 G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Florian, A. Giraldo, E. Heijne, P. Jarron, K. Kloukinas, A. Marchioro, P. Moreira, and W. Snoeys, “Radiation Tolerant VLSI Circuits in Standard Deep Submicron CMOS Technologies for the LHC Experiments: Practical Design Aspects,” IEEE Transactions on Nuclear Science, Vol. 46, pp. 1690-1696 (1999). 11 R.C. Lacoe, J.V. Osborn, R. Koga, S. Brown, and D.C. Mayer, “Application of Hardness-By-Design Methodology to Radiation-Tolerant ASIC Technologies,” IEEE Transactions on Nuclear Science, Vol. 47, pp. 2334-2341 (2000). 12 J.V. Osborn, R.C. Lacoe, D.C. Mayer, and G. Yabiku, “Total-Dose Hardness of Three Commercial CMOS Microelectronics Foundries,” IEEE Transactions on Nuclear Science, Vol. 45, pp. 1458-1463 (1998).

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aPPendix c  detect and correct a single error in a 16-bit word using the common “Hamming code” method requires the insertion of six additional bits. Thus, the error detection and correction technique requires a significantly greater number of memory bits to store a given amount of information. Circuit designers use computer-aided design tools to define and verify the final circuit layout, to perform logical simulation of the design, to identify potential failure modes, and to perform static and dynamic timing simulations. These tools use so-called “cell libraries” to simplify the design process as much as possible. Each library is a collection of individual circuit elements that includes functional and performance information about each element. Effective use of RHBD requires that knowledge of the behavior of the circuits in the space environment be incor- porated into the computer-aided design tools. For instance, the programs would need to simulate the electrical behavior of the transistor switch in a radiation environment based on the structure of the device and the physics of the radiation interactions.13 Rad-hard cell libraries are developed and maintained such that they will in- clude provisions for reliable operation in harsh environments. A number of cell libraries will probably be needed for each CMOS generation to meet the needs of a range of space programs operating in various orbits, and with a range of reli- ability, survivability, and cost requirements. Funding for libraries with the most stringent requirements—and thus the smallest markets—must be generated by the customer community.14 Commercial foundries typically provide the starting material for all electronic components manufactured in their processing facilities; however, nonstandard starting materials incorporating epitaxial layers or insulating substrates, for exam- ple, may enhance radiation immunity. The part supplier and the selected foundry may agree to substitute appropriate starting materials to provide additional levels of radiation hardness. Each foundry typically uses proprietary procedures developed over many years; however, nonstandard processing steps involving, for example, novel implants or modifications of layer thicknesses may help enhance radiation immunity. In this approach the RHBD part supplier and the selected foundry may agree to substi- tute or augment appropriate manufacturing steps to provide additional levels of radiation hardness. NASA has been employing design-hardening concepts in various projects. The Europa satellite, for example, will be exposed to more than 6 megarads over the life of the mission. To meet this high total-dose requirement, NASA is using rad-hard 13Available at http://www.aero.org/publications/crosslink/summer2003/index.html. Last accessed on March 25, 2010. 14 Ibid.

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seeing Photons  processors along with several digital and analog circuits designed using redundancy and other RHBD techniques. For the ROIC radiation hardness by design has quickly evolved from a concept to a strategy that may well redefine the way electronic components are procured for defense space systems. Companies have demonstrated that RHBD techniques can provide immunity from total-dose and single-event effects in commercially produced circuits. CAD tools that can model these radiation effects and cell li- braries that use a range of these techniques have been developed at a number of government agencies, universities, and private companies during the past several years, culminating in the commercial production of RHBD memories, micropro- cessors, and application-specific integrated circuits that are being specified. The infrastructure needed to make RHBD a mainstream procurement approach is gradually being developed.15 In addition to the ROIC performance, the detector performance is also im- pacted by radiation due to different layers ionizing, increase in dark currents due to charge carrier generation etc. The detector response depends on numerous factors such as detector material type, growth process, detector design, detector fabrication, and defects arising thru these different steps. The detector response is not characterized in isolation but together with the ROIC as a FPA. An example is observed by Hubbs et al where they discuss changes in the lateral diffusion length in HgCdTe detectors in a proton environment for LWIR detectors. They found that the non-ionizing energy loss (NIEL) in HgCdTe provides a frame work for estimat- ing responsivity degradation in LWIR MCT detectors due to on-orbit exposure from protons. They found that their comparison of the responsivity degradation at different proton energies suggested that the atomic columbic interaction of the protons with the MCT detector is likely the primary mechanism responsible for the degradation in the responsivity at proton energies below 30 MeV.16 15Available at http://www.aero.org/publications/crosslink/summer2003/index.html. Last accessed on March 25, 2010. 16 John E. Hubbs et al., “Lateral Diffusion Length Changes in HgCdTe Detectors in a Proton Envi - ronment,” IEEE Transactions on Nuclear Science, Vol. 54, no. 6 (2007), p. 2435.