A number of advances, such as putting more processing into a pixel or making a smaller pixel, depend on continued improvements in silicon complementary metal oxide semiconductor (CMOS) process technology, driven by the semiconductor industry’s push to stay on the Moore’s law scaling curve. It is worth noting that device scaling is becoming increasingly technically challenging and expensive and that physical limits are becoming real roadblocks to CMOS scaling. Many process technologies developed for 65 nm, 45 nm, or 32 nm, while excellent in terms of digital circuit performance, are less than ideal for the analog portions of a pixel. They may have high transistor leakage levels and very limited dynamic range due to smaller voltage swings, thus limiting performance. Accordingly, device scaling is likely to be exploited by adding digital functionality to pixels. As more advanced CMOS process technologies are used, the cost per transistor drops, but the cost per area of CMOS chips increases. This, in turn, carries negative implications for focal planes that require physically large areas.

Advanced processes are also costly and have large nonrecurring expenses associated with design, mask generation, and initial design and debugging, making it expensive to develop custom devices needed only in small volumes. It is also worth noting that changes in the lithography processes used at smaller feature sizes require specialty techniques, such as field stitching, to produce large-area devices that exceed the field size of modern lithography tools. In short, while CMOS scaling will dramatically shape the design options for advanced focal planes, significant learning and innovation will be required to apply these advanced technologies optimally. In many cases, visible sensor applications do not benefit from the high-volume manufacturing imperatives that both drive and allow amortization of the increasing tool cost that accompanies CMOS scaling.

A number of areas in which near-term technology advances are expected include ultralarge-format arrays; mosaic tiling technologies; pixel size reduction; smarter pixels and on-focal plane processing; improved three-dimensional (3-D) integration and hybridization; higher-operating-temperature devices; multicolor pixels; improved short-wavelength infrared (SWIR) arrays; photon counting technologies and lower readout noise; curved focal surfaces; lower-power operation; radiation hardening; cost reduction; and improved cooler technology.


With respect to areas in which near-term technology advances are expected, this section examines each of the advances and addresses benefits, risks or drawbacks, impact on system performance, and implications for military applications of the expected advances.

The National Academies | 500 Fifth St. N.W. | Washington, D.C. 20001
Copyright © National Academy of Sciences. All rights reserved.
Terms of Use and Privacy Statement