Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions


ROBERT H. DENNARD, MEMBER. IEEE, FRITZ H. GAENSSLEN, HWA-NIEN YU, MEMBER, IEEE, V. LEO RIDEOUT, MEMBER, IEEE, ERNEST BAS SOUS, AND ANDRE R, LEBLANC, MEMBER, IEEE

Classic Paper


This paper considers the design, fabrication, and characterization of very small MOSFET switching devices suitable for digital integrated circuits using dimensions of the order of 1 μ. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET’s with channel lengths as short as 0.5 μ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.

I. LIST OF SYMBOLS

α

Inverse semilogarithmic slope of subthreshold characteristic.

D

Width of idealized step function profile for channel implant.

ΔWf

Work function difference between gate and substrate.

Si, ∈OX

Dielectric constants for silicon and silicon dioxide.

Id

Drain current.

k

Boltzmann’s constant

κ

Unitless scaling constant.

L

MOSFET channel length.

µeff

Effective surface mobility.

ni

Intrinsic carrier concentration.

Na

Substrate acceptor concentration.

Ψs

Band bending in silicon at the onset of strong inversion for zero substrate voltage.

Ψb

Built-in junction potential.

q

Charge on the electron.

Qctt

Effective oxide charge.

tox

Gate oxide thickness.

T

Absolute temperature.

Vd, Vs, Vg, Vsub

Drain, source, gate and substrate voltages.

Vds

Drain voltage relative to source.

Vs—sub

Source voltage relative to sustrate.

Vt

Gate threshold voltage.

Ws, Wd

Source and drain depletion layer widths.

W

MOSFET channel width.

This paper is reprinted from IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-9, no. 5, pp. 256–268, October 1974.

Publisher Item Identifier S 0018-9219(99)02196-9.

II. INTRODUCTION

New high resolution lithographic techniques for forming semiconductor integrated circuit patterns offer a decrease in linewidth of five to ten times over the optical contact masking approach which is commonly used in the semiconductor industry today. Of the new techniques, electron beam pattern writing has been widely used for experimental device fabrication [1]-[4] while X-ray lithography [5] and optical projection printing [6] have also exhibited high-resolution capability. Full realization of the benefits of these new high-resolution lithographic techniques requires the development of new device designs, technologies, and structures which can be optimized for very small dimensions.

This paper concerns the design, fabrication, and characterization of very small MOSFET switching devices suitable for digital integrated circuits using dimensions of the order of 1 μ. It is known that reducing the source-to-drain spacing (i.e., the channel length) of an FET leads to undesirable changes in the device characteristics. These changes become significant when the depletion regions surrounding the source and drain extend over a large portion of the region in the silicon substrate under the gate electrode. For switching applications, the most undesirable “short-channel” effect is a reduction in the gate threshold voltage at which the device turns on, which is aggravated



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