Asian Research, U.S. Department of Commerce, the Deloitte Center for the Edge, and the Frontier Strategy Group.

Relevant publications include Indigenous Innovation and Globalization: The Challenge for China’s Standardization Strategy (2011) [now published in Chinese]; China’s Innovation Policy Is a Wake-Up Call for America (2011); A New Geography of Knowledge in the Electronics Industry? Asia’s Role in Global Innovation Networks (2009); Can Chinese IT Firms Develop Innovative Capabilities within Global Knowledge Networks? (2008); China’s Emerging Industrial Economy-Insights from the IT Industry (with Barry Naughton) (2007); Innovation Offshoring-Asia’s Emerging Role in Global Innovation Networks (2006); “Complexity and Internationalization of Innovation: Why is Chip Design Moving to Asia?", International Journal of Innovation Management, 2005; “Limits to Modularity: Reflections on Recent Developments in Chip Design”, Industry and Innovation, 2005; International Production Networks in Asia: Rivalry or Riches? (2000); and Technological Capabilities and Export Success: Lessons from East Asia (1998).

MARK D. HILL is a professor of computer science and electrical and computer engineering at the University of Wisconsin–Madison. Dr. Hill’s research targets computer design and evaluation. He has made contributions to parallel computer system design (e.g., memory-consistency models and cache coherence), memory-system design (caches and translation buffers), computer simulation (parallel systems and memory systems), software (e.g., page tables and cache-conscious optimizations for databases and pointer-based codes), and transactional memory. For example, he is the inventor of the widely used 3C model of cache behavior (compulsory, capacity, and conflict misses).

Dr. Hill’s current research is mostly part of the Wisconsin Multifacet Project that seeks to improve the multiprocessor servers that form the computational infrastructure for Internet Web servers, databases, and other demanding applications. The Multifacet work focuses on using the transistor bounty provided by Moore’s Law to improve multiprocessor performance, cost, and fault tolerance, while also making these systems easier to design and program.

Dr. Hill was named an ACM fellow (2004) for contributions to memory consistency models and memory system design, elevated to a fellow of the IEEE (2000) for contributions to cache memory design and analysis, and was awarded the ACM SIGARCH Distinguished Service Award in 2009. He has won three important University of Wisconsin awards: Kellett Mid-Career in 2010, Vilas Associate in 2006, and Romnes Faculty Fellowship in 1997. He co-edited Readings in Computer Architecture in 2000, is coinventor of more than 30 U.S. patents (several of which have been coissued in the European Union and Japan), was an ACM SIGARCH director (1993–2007), and won a National Science Foundation Presidential Young Investigator award in 1989. He is coauthor of five papers selected by IEEE Micro Top Picks and co-won the best paper award at the International Conference on Very Large Databases (VLDB) in 2001. He has held visiting positions at Advanced Micro Devices (2011), University of Washington (2011), Columbia University (2010), Polytechnic University of Catalonia (2002–2003) and Sun Microsystems (1995–1996). Dr. Hill earned a Ph.D. in computer science from the University of California, Berkeley, in 1987, an M.S. in computer science from UC Berkeley in 1983, and a B.S.E. in computer engineering from the University of Michigan–Ann Arbor in 1981.

STEPHEN W. KECKLER is the senior director of architecture research at NVIDIA and professor of both computer science and electrical and computer engineering at the University of Texas (UT) at Austin, where he has served on the faculty since 1998. His research interests include parallel computer architecture, technology-scalable architectures, very-large-scale integration (VLSI) design, high-performance computing, energy-efficient computing, and on-chip interconnection networks. He has developed both commercial chips at Intel and parallel computing prototype chips at MIT and UT Austin. At MIT, he was the principal architect of the M-Machine multicomputer, a research machine that was one of the first multicore processors and included extremely efficient inter-thread communication and synchronization mechanisms. His research team at UT Austin developed scalable parallel processor and memory system architectures, including nonuniform cache architectures; explicit data graph execution processors, which merge dataflow execution with sequential memory semantics; and micro-interconnection networks to implement distributed processor protocols. His research team at NVIDIA is developing extreme energy-efficient computing technologies for massively parallel chips and systems.

Dr. Keckler was named fellow of the ACM (2011) for contributions to computer architectures and technology modeling, and was elevated to a fellow of the IEEE for contributions to computer architectures and memory systems. He received the 2003 ACM Grace Murray Hopper Award for ground-breaking analysis of technology scaling for high-performance processors that sheds new light on the methods required to maintain

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