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OCR for page 69
E
Dennard Scaling and Implications
T he following description was taken from the 2010
National Research Council Computer Science and
Telecommunications Board (CSTB) report The
Future of Computing Performance: Game Over or Next
Level?1
decreases by 1/ because the smaller gates make all the
wires shorter and capacitance is proportional to length.
Therefore, the power requirements per unit of space on
the chip (mm2), or energy per second per mm2, remain
constant:
"In a classic 1974 paper, reprinted in Appendix D, Power = (number of gates)(CLoad/gate)(Clock Rate)(Vsupply2)
Robert Dennard et al. showed that the MOS Power density = NgCloadFclkVdd2
transistor has a set of very convenient scaling Ng = CMOS gates per unit area
properties.10 The scaling properties are shown in Cload = capacitive load per CMOS gate
Table 3.1, taken from that paper. If all the voltages Fclk = clock frequency
in a MOS device are scaled down with the physical Vdd = supply voltage
dimensions, the operation of the device scales in a Power density = (2)(1/)()(1/)2 = 1
particularly favorable way. The gates clearly become
smaller because linear dimensions are scaled. That That the power density (power requirements per unit
scaling also causes gates to become faster with space on the chip, even when each unit space contains
lower energy per transition. If all dimensions and many, many more gates) can remain constant across
voltages are scaled by the scaling factor ( has generations of CMOS scaling has been a critical property
typically been 1.4), after scaling the gates become underlying progress in microprocessors and in ICs in
(1/)2 their previous size, and 2 more gates can be general. In every technology generation, ICs can double
placed on a chip of roughly the same size and cost as in complexity and increase in clock frequency while
before. The delay of the gate also decreases by 1/, consuming the same power and not increasing in cost.
and, most importantly, the energy dissipated each Given that description of classic CMOS scaling, one
time the gate switches decreases by (1/)3. To would expect the power of processors to have remained
understand why the energy drops so rapidly, note constant since the CMOS transition, but this has not been
that the energy that the gate dissipates is the case. During the late 1980s and early 1990s, supply
proportional to the energy that is stored at the output voltages were stuck at 5 V for system reasons. So power
of the gate. That energy is proportional to a quantity density would have been expected to increase as
called capacitance11 and the square of the supply technology scaled from 2 mm to 0.5 mm. However, until
voltage. The load capacitance of the wiring recently supply voltage has scaled with technology, but
power densities continued to increase."
1
NRC, 2011, The Future of Computing Performance: Game
Over or Next Level?, Washington, D.C.: The National Academies
Press (available online at http://www.nap.edu/catalog.php?record_
id=12980).
69
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