National Academies Press: OpenBook

Chip Seal Best Practices (2005)

Chapter: Chapter Eight - Chip Seal Performance Measures

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Suggested Citation:"Chapter Eight - Chip Seal Performance Measures." National Academies of Sciences, Engineering, and Medicine. 2005. Chip Seal Best Practices. Washington, DC: The National Academies Press. doi: 10.17226/13814.
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Page 56
Suggested Citation:"Chapter Eight - Chip Seal Performance Measures." National Academies of Sciences, Engineering, and Medicine. 2005. Chip Seal Best Practices. Washington, DC: The National Academies Press. doi: 10.17226/13814.
×
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Page 57
Suggested Citation:"Chapter Eight - Chip Seal Performance Measures." National Academies of Sciences, Engineering, and Medicine. 2005. Chip Seal Best Practices. Washington, DC: The National Academies Press. doi: 10.17226/13814.
×
Page 57
Page 58
Suggested Citation:"Chapter Eight - Chip Seal Performance Measures." National Academies of Sciences, Engineering, and Medicine. 2005. Chip Seal Best Practices. Washington, DC: The National Academies Press. doi: 10.17226/13814.
×
Page 58
Page 59
Suggested Citation:"Chapter Eight - Chip Seal Performance Measures." National Academies of Sciences, Engineering, and Medicine. 2005. Chip Seal Best Practices. Washington, DC: The National Academies Press. doi: 10.17226/13814.
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Page 59

Below is the uncorrected machine-read text of this chapter, intended to provide our own search engines and external engines with highly rich, chapter-representative searchable text of each book. Because it is UNCORRECTED material, please consider the following text as a useful but insufficient proxy for the authoritative book pages.

INTRODUCTION Defining chip seal performance criteria, and how to quantify them, is perhaps the most difficult consideration for any pub- lic owner with chip seal projects. Throughout the literature review, an effort was made to identify any particular accep- tance criteria or performance specifications that would illus- trate chip seal performance measures. The objective of this chapter is to identify performance specifications and become familiar with their attendant performance measures. Two separate schools of thought in regard to performance mea- surement have been identified. Chip seal performance is pri- marily either measured quantitatively through engineering principles or rated qualitatively through expert visual assess- ment. The literature review and survey results discovered lit- tle beyond measuring skid resistance for quantitative chip seal performance measurements in North America, but quan- titative performance measures are widespread in Australia, New Zealand, South Africa, and the United Kingdom. ENGINEERING-BASED PERFORMANCE INDICATORS Quantitative chip seal performance measurement techniques were evaluated by a study at the Pennsylvania Transportation Institute (Roque et al. 1991). Performance measurements of rutting and roughness are widely used on other wearing courses such as asphalt pavement. Chip sealed surfaces look and perform differently from asphalt pavement surfaces; therefore, their performance needs to be based on a different set of visual evaluation methods than for asphalt pavements (Walker 2001). As such, asphalt pavement performance mea- surements are not often applicable to measuring chip seal per- formance, because none of those methods will formally mea- sure the two most common chip seal distresses, bleeding and raveling. Measuring skid resistance and measuring texture depth are the only two repeatable and objective quantitative methods that may be applicable. Skid Resistance Skid resistance, an important safety characteristic for all roads, can be used as a performance measure on chip sealed surfaces (Roque et al. 1991). The skid resistance or friction, which develops between a vehicle’s tires and the surface of the road, is a function of two components, macrotexture and micro- 56 texture (Abdul-Malak et al. 1993). Basically, the microtexture is determined by the frictional properties of the aggregate, whereas the macrotexture is determined by the size, shape, and spacing of the aggregate particles (Abdul-Malak et al. 1993). Although there are other acceptable methods for measuring skid resistance, the most common method for a chip seal is according to ASTM E274, Standard Test Method for Skid Resistance of Paved Surfaces Using a Full-Scale Tire (Seneviratne and Bergener 1994). This method measures the sliding friction force developed between a tire and roadway surface and expresses the result as a skid number. The justifi- cation behind using skid numbers as a determinant of chip seal performance, and thus also the service life of the chip seal, is that skid numbers drop over time owing to deterioration of the pavement’s surface texture (Seneviratne and Bergener 1994). Most agencies have a specified cycle on which skid resistance is measured as a part of their pavement management system. These data are invaluable to making the decision as to which roads to chip seal. Texture Depth The literature review identified several methods for measur- ing a pavement’s macrotexture (Abdul-Malak et al. 1993). Of these, the survey results indicated that the only measurement with widespread acceptance by the international respondents is the sand patch method (ASTM E965). In the Pennsylvania study, the mean texture depth (MTD) as obtained by the sand patch method was found to give the best indication of chip seal performance, in addition to being an objective manner of comparing chip seals on a relative basis (Roque et al. 1991). Aggregate retention and resistance to bleeding are both evi- dent by evaluating MTD. The study in Pennsylvania proposed that the rationale for using MTD as the best indication of performance is that greater macrotexture generally implies greater skid resistance (Roque et al. 1991). This same study found that the MTD, as indicated by macrotexture, decreased with time as a result of both aggregate wear and embedment. Assuming such, chip seal deterioration models can evalu- ate the effects of different variables on expected chip seal life (Roque et al. 1991). The study in Pennsylvania, which pro- poses that MTD is the best indication of chip seal performance, is in agreement with New Zealand and United Kingdom philosophies in the development of performance specifications (Design Guide . . . 2002; Notes for the Specifications . . . 2002). Texture depth appears to be the performance measure of choice. CHAPTER EIGHT CHIP SEAL PERFORMANCE MEASURES

57 Engineered Performance Specifications In a previous NCHRP synthesis, a performance specification was defined as “how the finished product should perform over time” (Chamberlain 1995). Specification of design life expec- tations is an effective means of determining long-term chip seal performance. The most prominent example of a chip seal performance specification is Transit New Zealand’s, Notes for the Specification of Bituminous Reseals (P17) (2002). The philosophy behind this specification is that the texture depth after a 12-month inspection is the most accurate indication of the performance of the chip seal for its remaining life. The New Zealand specification contends that “the design life of a chip seal is reached when the texture depth drops below 0.035 in. (0.9 mm) on road surface areas supporting speeds greater than 43 mph (70 km/h)” (Notes for the Specifica- tions . . . 2002). The deterioration models developed in New Zealand have directed the P17 specification to require the fol- lowing minimum texture depth 1 year after the chip seal is completed, using Eq. 4. Td1 = 0.07 ALD log Yd + 0.9 (4) where Td1 = texture depth in 1 year (mm), Yd = design life in years, and ALD = average least dimension of the aggregate. The entire specification is based on the assumption that chip seals fail as a result of bleeding (Notes for the Specifications . . . 2002). Within the specification, noise or aesthetic factors are the only reasons for specifying a maximum texture depth. The final acceptance is based on the achievement of the required texture depth, without any significant chip loss. More on the detailed methodology behind New Zealand’s performance- based specification can be found in Appendix D. QUALITATIVE PERFORMANCE INDICATORS It must be noted here that although the measurement of skid resistance is common throughout North America, the researchers could find no instances where public highway agencies were using skid numbers to directly evaluate the performance of chip seals. Skid numbers, however, were used as trigger points for making the decision to apply a new chip seal on a road. Therefore, the only true form of chip seal performance measure identified among the North American survey respondents was the rating of visual distresses that materialize during the design life of the chip seal. Figure 58 shows the distress modes that survey respondents commonly identified in their chip seals. It is obvious that raveling and bleeding are widespread dis- tresses. The literature review shows that chip seal perfor- mance is generally a function of the following factors (Elmore et al. 1995a and b): • Quality of design, • Quality and consistency of construction, • Quality and consistency of materials, • Environmental conditions, and • Traffic conditions. Visual Surface Ratings Chip seal performance is commonly measured through a sys- tem that provides for visual rating of the chip seal’s condition. Visual rating of chip seal performance by apparent distress modes is justified because these distresses generally determine the life of a chip seal. The role that aesthetics play in the chip seal process also makes objective decision making difficult. The idea that the road should look good after it is completed is an important driver of chip seal performance perception (Gransberg et al. 1998). Visual performance assessment is irreplaceable, even though it is inherently subjective. There- fore, agencies should ensure that experienced personnel are employed to make these assessments. Furthermore, there is evidence that technical vocabulary for chip seal performance is considerably variable within a state, let alone on national and international levels. One can see how establishing any objec- tive metric to assist inspection forces based on visual assess- ment is problematic (Gransberg et al. 1998). Visible Chip Seal Distress Chip seals generally deteriorate as a result of binder oxida- tion, wear and polishing of aggregate, bleeding, and aggre- gate loss (Sprayed Sealing Guide 2004). These processes are expressed graphically in the Austroads chips seal distress model (Figure 59). Performance evaluation pertaining to surface appearance, reflective cracking, aggregate loss, and texture loss can all be subjectively observed and rated based on their extent and severity of distress. As evident from the both the survey responses and confirmed in the literature review, bleeding and raveling are the most common distresses found with a chip sealed surface (Benson and Gallaway 1953; Holmgreen et al. 1985). 81% 67% 49% 0% 20% 40% 60% 80% 100% Bleeding Raveling Bleeding and Raveling FIGURE 58 Most common distress modes identified by survey respondents.

Bleeding Bleeding is normally distinguished by black patches of excess binder appearing on the surface of the chip seal (Gransberg et al. 1998). In other words, a bleeding surface has a smooth and slick appearance where the aggregates are less visible. Figure 60a and b illustrates this condition. Bleeding is caused by either an excess of binder in proportion to the aggregate or where the aggregate is forced to achieve levels of embedment beyond the design embedment depth (Sprayed Sealing Guide 2004). Such distress is usually observed in the wheelpaths where the repetitive load cycle of tires causes subsequent embedment of aggregates. Bleeding problems are generally associated with high binder rates and nonuniform aggregate gradations, and bleeding is accelerated by high temperatures (Gransberg et al. 1998). During hot weather, underlying asphalt layers may soften to a point that these aggregate particles may penetrate into the underlying binder, leaving excess asphalt on the surface (Senadheera and Khan 2001). 58 Raveling Raveling is the loss of aggregate from the chip seal’s surface. Such chip seal surfaces have a very irregular appearance, because the surface is not completely covered by the aggre- gate, as shown in Figure 61a and b. Raveling occurs when the bond between the aggregate and binder fails, causing the aggregate to become displaced from the binder. Raveling is most common in areas outside of the wheelpaths where embed- ment is lowest (Senadheera and Khan 2001). Defects In addition to the distresses that form from the deterioration of the chip seal over time, two common defects need to be mentioned: poor construction and placing a chip seal on a structurally inadequate pavement. Such defects commonly cause the chip seal to fail before its planned service life. FIGURE 59 Chip seal distress model (adapted from Sprayed Sealing Guide 2004). (a) (b) FIGURE 60 (a and b) Results of excess binder—Bleeding in wheel paths.

59 Streaking, also known as drilling, is the formation of alter- nating lean and heavy lines (streaks) in the chip seal that result from a failure to apply the binder uniformly across the road’s surface (Senadheera and Khan 2001). Streaking, shown in Figure 62, is mostly an aesthetic problem, but it can reduce the design life of the chip seal when aggregate loss begins to take place. Rutting on the pavement surface is the result of deformation in the layers of the pavement’s structure (Senadheera and Khan 2001). It is directly related to the structural strength of the underlying material. As one can see from Figure 63, chip seals will not benefit a pavement susceptible to rutting; these pave- ments need rehabilitation or reconstruction. Additionally, seal- ing a rutted pavement will likely cause the ruts to be flooded with binder and fail as the result of bleeding in a very short time. Ohio Visual Evaluation Method For integration into Ohio’s Supplemental Specification 882, Chip Seal with Warranty, the state has established the fol- lowing performance criteria for chip seal construction, as detailed in Table 13. This table is a particularly useful way to quantify the subjective nature of visual distress assessment by demanding remediation of the distress when the illustrated extent of severity is met. In addition, the Ohio DOT prescribes the following chip seal acceptance criteria: • Finished surface has minimal tears and binder streaking. • Joints appear neat and uniform without buildup, uncovered areas, or unsightly appearance. • Longitudinal joints have less than a 2 inch (50 mm) overlap. (a) (b) FIGURE 61 (a and b) Results of aggregate loss—Raveling. FIGURE 62 Streaking (Senadheera and Khan 2001). FIGURE 63 Rutting (Asphalt Surface Treatments—Construction Techniques 1988).

• Transverse joints have no more than 0.25 inch (6.5 mm) dif- ference in elevation across the joint as measured with a 6 foot (2 m) straightedge. • Chip seal edge is neat and uniform along the roadway lane, shoulder, and curb lines. • Chip seal edge has no more than 2 inches (50 mm) variance in any 100 feet (30 m), along the roadway edge or shoulder (Ohio DOT 2002). PERFORMANCE CONCLUSIONS AND BEST PRACTICES The performance of chip seals is affected by a variety of factors related to design, materials, and construction. The literature review and survey results confirm that bleeding by far leads the predominant distress category. Therefore, an effort needs to be made to quantitatively measure bleed- ing and identify any means that can minimize it. Chip seal conditions deteriorate with age, and as such, measuring tex- ture is a useful tool in developing a pavement condition index for the seal. 60 Chapter four discusses performance risk distribution in chip seal contracts. This is extremely important in the context of this chapter, in that performance risk can be measured only by per- formance indicators. As a performance indicator’s measure- ment grows more objective, the agency’s capacity to enforce a construction warranty increases. Therefore, the following best practices were identified from this chapter’s analysis: 1. An approved method, such as the sand patch method, to measure chip seal macrotexture can furnish an objec- tively measured chip seal performance indicator. 2. The use of the chip seal deterioration model expressed in the New Zealand P17 Specification will furnish an objective definition of chip seal performance based on engineering measurements. 3. The two aforementioned methods can be supplemented with a continued visual distress rating based on the Ohio DOT’s chip seal performance criteria, as shown in Table 13. Defect Severity Extent Surface Patterns Severe—light and heavy lines Greater that 40% of segment over the pavement surface length affected, continuous, or localized Bleeding/Flushing Moderate—excess binder on Greater than 5% of segment surface (loss of stone/tire length affected continuously contact) not subject to or total of 20% localized wearing off quickly problems Loss of Aggregate Moderate—patches of aggregate Greater than 10% of segment loss length affected continuously or total of 20% localized problems Source: Supplemental Specification 882, Chip Seal with Warranty 2002. TABLE 13 OHIO DOT’s CHIP SEAL PERFORMANCE CRITERIA, 2002

Next: Chapter Nine - Best Practice Case Studies »
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TRB’s National Cooperative Highway Research Program (NCHRP) Synthesis 342: Chip Seal Best Practices examines ways to assist in the development and implementation of pavement preservation programs by identifying the benefits of using chip seal as part of a preventive maintenance program and by highlighting advanced chip seal programs in use around the world. The report includes approximately 40 best practices in the areas of chip seal design methods, contract administration, equipment practices, construction practices, and performance measures. According to the report, the increased use of chip seals for maintenance can be a successful, cost-effective way of using preventive maintenance to preserve both low-volume and higher-volume pavements.

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