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Chapter 3 PACKAGING STRATEGIES AND ASSOCIATED MATERIALS AND PROCES S REQUIREMENTS The increase in system performance that modern VLSI processing technology can provide usually is not realized because electronic packaging and assembly techniques practiced today negate much of the potential performance gain. The situation arises because the lengths of chip- to - chip interconnections on various packaging levels have not shrunk at nearly the same rate as on-chip interconnections, and the package-associated total wiring off-chip often exceeds the length of on-chip wiring by many times. To minimize deleterious package effects, it is necessary to first reduce the average chip-to-chip interconnection length, i.e., chips have to be placed much closer to each other. It is also necessary to use materials with minimum dielectric constant for insulators in the interconnection network. Further- more, circuit noise must be minimized, and there must be sufficient wirability at the various packaging levels to interconnect all the I/Os within a relatively few layers. This chapter reviews current packaging approaches, with emphasis on the limitations that make them insufficient, and projected future packaging strategies, with focus on the packaging materials and processes that are required to make them a reality. Comparisons of packing dens ity, performance, and cost are made for various approaches. PRESENT PACKAGING APPROACHES The two main approaches currently used in the United States to achieve high-density electronic packaging are the printed wiring board (PWB) approach and the thick- film multichip module (MClI) approach using ceramic and polyimide dielectrics. In the PWB approach , s ingle - chip modules (SCMs), the first packaging level, are assembled on a printed wiring board, the second packaging level, as individual packages by either through-hole or surface mounting using soft solder joints. In the thick-film lICM approach, on the other hand, multichip modules contain multiple bare chips j ointly packaged in a ceramic package that is constructed by multilayering thick film conductor layers and ceramic dielectric layers. It is these MCMs (level 1.5) that are then in turn mounted on the PWB (second level). A third technique employed by NEC (Japan) since 1983 uses successive thin-film wiring layers. 41

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42 Single-Chip Modules on Printed Wiring Boards In the PWB approach, a printed wiring board is used with multiple x and y conductor planes appropriately spaced between ground and power planes. The conductor run width is typically 5 to 10 mils, and the thickness is of the order of 1 milt The epoxy-glass dielectric layers are typically 5 mils thick. Plated through-holes (PTHs) connect the various conductor planes and are arranged on a regular grid with a hole-to-hole spacing of 100 mils. Chip dimensions are conventionally discussed in terms of micrometers (pm). Printed wiring interconnection structures are usually described in terms of mils, i.e., 0.001 in. Advanced interconnection structures may involve both units. One mil is equal to 25.4 ~m. Geometric Limitations: To increase the packaging density, the systems designer attempts to place the semiconductor packages as close together as possible. The interconnection vehicle, the printed wiring board, is normally offered with a 100-mil PTH grid and a wirability in the neighborhood of 40 lines per inch per layer. Many interconnect layers are possible, but 2- to 8- layer boards are most common. Since each package pin must normally be connected to one PTH, the packaging density is limited approximately by the PTH density (i.e., 100 pins per square inch). Thus, a 100-pin package occupies at least 1 square inch, even if the package outline per se is much smaller. Pin grid arrays (PGAs) are the most efficient, since the pin spacing on the package exactly corresponds to the PTH grid on the board. Of course, not all PTHs on the board may be occupied by package pins, since a rim of about 250 mils must be kept open around each package to facilitate package mounting, removal, access to test pads, engineering change capability, decoupling capacitors, etc. Surface-mounted, peripherally-leaded packages can be just as density-efficient if the package leads can be wired to the PTHs underneath the package. This normally is possible unless the package pin count is too great or the lead pitch is too coarse. The reason is that, to be able to route underneath the package to reach the appropriate PTH, most of the conductor runs must squeeze between two PTHs on the distribution layer of the board. If a surface- mounted package has more than 256 pins, then, because of the maximum permitted wiring density of 40 lines per inch, the innermost PTHs underneath the package can no longer be reached, and at least some package pins must be routed to PTHs outside the package outline. This is true for square package outlines. If rectangular outlines are used for surface-mounted packages, a packaging density equivalent to that for PGAs can be achieved, provided that no more than 64 pins are placed on the short edge and the pin spacing is not larger than 25 mils. Since the PTH grid is the ultimate factor that limits the packaging density in any case, a pin pitch less than 25 mils for square-mounted packages is unnecessary, because this will not lead to increased density on a 100-mil PTH grid board. Thus, even "chip-on-board" packaging techniques do not lead to a higher packaging density.

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43 Board assembly of surface-mounted packages with lead pitches as fine as 25 mils already presents many problems, such as lead control, solder control, placement accuracy, and inspectability. These factors may force the use of coarser lead pitch (e.g., 50 mile), if the number of PTHs contained in the area underneath the package exceeds the number of package leads. Even when optimum outlines are used, only about 50 to 75 percent of the available PTH grid can be occupied by package pins. Clearly, higher packaging density can be achieved with a PTH spacing of less than lOO mils, but a finer grid is not easily achieved because of the required hole-drilling position accuracy, which is particularly critical in multilayer boards. Furthermore, PWB technology is a well-entrenched manufacturing technology in which considerable investment has already been made. It is likely that there would be resistance to the introduction of new techniques that require drastic manufacturing changes. The introduction of more blind vies also can lead to somewhat higher density. Pin Limitations at the Interface to the Next Packaging Level: The systems designer normally is constrained to present a relatively small interface to the outside world. Thus, a state-of-the-art printed circuit board today is typically limited to a 200- to 400-pin interface to the next packaging level, depending on board size and edge-connector technology. Since even 2 or 3 VLSI chips together can exceed this number of I/Os, a significant number of chips can be interconnected on the PWB only if the pin- to-gate ratio can be drastically reduced, normally well below that predicted by Rent's rule. For example, for an array processor design using a mix of 100 VLSI logic and memory chips for a total of 4.36 million gates, the designer is presented with 8600 signal I/O and power and ground pins on the chip level. These must be reduced to a few hundred by a proper interconnect design. Perhaps 200 of these can be brought out through the board edge connectors to the backplane. The remaining pins must be interconnected on the board. This pin reduction is achieved by interconnecting the appropriate mix of logic, memory, and glue chips, i.e., counters, latches, shift registers, and multiplexers. Although this is usually done at the expense of the number of available data paths, some performance loss is recouped because of shorter interconnections and fewer required PWBs, backplanes, and cables. Rent's rule can be broken at any level of integration. The microprocessor chip is an example of the breaking of Rent's rule in its original form for gate arrays on the chip level. The multichip-module approach to packaging, on the other hand, allows a delay in breaking of Rent's rule until a much higher level of integration is achieved. This is always an advantage because it preserves many parallel data paths, even at very high levels of integration, and thus offers higher systems performance and greater architectural flexibility. Materials Limitations: Considerable differences exist in the thermal - coefficient of expansion (TCE) between the PWB and the common first-level packages. Thus, the ICE of an FR-4 PWB is 17 ppm in the XY direction and 60 in the Z direction. Both of these are higher than the TCEs encountered in

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most packages, particularly the ceramic packages that are normally used to house high-pin- count VLSI chips . These differences cause large plastic strain excurs ions between board and packages and can lead to metallurgical fatigue in the solder j oints and the copper in the plated through-holes . There is also the tendency of the PWB to warp during assembly because of the use of low-Tg polymers . Thick- Film Multichip Modules Us ing Ceramic Dielectrics An alternative approach to the density problem is to insert another packaging; level between the single-chip module (level 1) and the printed wiring board ~ level 2 ), namely the multichip module (MCM), often called level 1.5. The added level is not limited by ache PTH grid and thus is capable of a much finer interconnection grid and much higher wirability than the printed wiring board, and it can also provide most of the interconnections between chips" This greatly reduces the interconnection effort required at the PWB level. Chips can be placed much closer together, and, in fact, there is normally no room for first-level packages at all; bare chips directly bonded to the MCM substrate must be utilized. In the multichip module, bare chips are interconnected on a subs bate with substantially finer conductor lines, smaller dielectric thicknesses, and denser via grid than on a board. In addition, the substrate is not subj ect to conventional PWB design rules and assembly restrictions. Multichip-module technologies can be grouped roughly into thick-film multichip modules using ceramic dielectrics and thin-film modules using polymeric dielectrics. The thick-film approach has been used extensively in the past, whereas the thin- film approach is just emerging. (The thin-film wiring approach has been employed extensively by NEC.) The thick- film approach is in turn divided into two groups, the multilayer hybrid and the co- fired ceramic and conductor block. In the first, the thick-film multilayer hybrid, both the metallic conductor layers and the dielectric layers are appli ed by silk screening. The appropriate metal or dielectric ink is applied to a sintered ceramic substrate by use of a squeegee through thick- film screen masks that define the location of the conductor runs and vies. After screening, these layers are fired at temperatures from 650 to 950C. The metallic thick-film inks normally contain noble metal (Pt. Au, Ag, Pd) particles and glass frit particles suspended in an organic binder. The glass frit anchors the metal particles firmly to the substrate during the firing process in an oxidizing atmosphere. Non-noble metal (Cu. Ni) inks are sometimes used instead of noble ones. These employ fluxes, such as CdO, to ensure adhesion to the substrate, but must be fired in a nonoxidizing atmosphere to avoid tarnishing the metal . Generally, control of the firing process is poor. Dielectric inks contain glass and ceramic particles that fuse together to give continuous , nearly pinhole-free films. Many layers can be printed and fired in this way; however, yield considerations generally limit this approach to about 12 layers or fewer.

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45 While the thick-film multilayer approach has been used to interconnect VLSI chips, either as bare chips or packages in ceramic chip carriers, it can achieve only modest packaging density. Some of the reasons are: insufficient wirability; ~ poor registration accuracy; poor electrical conductivity of the conductor runs; high-dielectric-constant insulators; insufficient substrate flatness. The thick-film multilayer approach has found its most significant application in linear circuits where thick-film resistor functional-trimming requirements make this approach cost-efficient. The second thick-film, multichip approach currently in use employs a co- fired ceramic multilayer substrate that contains multiple conductor and dielectric levels fused into a three-dimensional block. Because of its mechanical stability, this approach has seen extensive application in high- density digital packaging, principally for central processors in computers. A packing density of 25 percent of a "solid block" is possible, although many tens of layers are required to achieve this. However, still greater densities are becoming more difficult because of the following: The refractory metal ink conductor line must be fairly wide (10 mils) to ensure sufficient electrical conductivity. As many as 50 layers have been manufactured, but the process is increasingly costly as layers are added. After firing and the resulting shrinkage, the location of any particular feature on the fused substrate is known only with limited accuracy. Flatness control is difficult. . The process is feasible only in high-volume production that requires large investments. FUTURE PACKAGING STRATEGIES features: A successful packaging strategy will have to embody the following much higher functional density, managing very high pin counts,

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46 ~ distributed power supplies to allow high-voltage power delivery, J many simultaneously switching I/Os, heroic cooling approaches at higher power densities and less space allotted for the cooling fluid, some approach for high-density Z-direction wiring, more serial data transmission by optical, microwave, or other links for data communication over longer distances, optical clock signal distribution to control skew, and reasonable costs. The fundamental building block is the replaceable high-density module, mounted on a second-level board. Packaging approaches will differ from each other principally in the choice of the multichip module alternatives. The two most important alternatives are the thin-film multichip module and wafer-scale integration. Thin-Film Multichip Modules Using Polymeric Dielectrics The new packaging approaches now emerging, intended to increase the packing density to well above 25 percent, all attempt to employ processes analogous to those used in the processing of the VLSI chips themselves. In particular, the interconnecting conductor pattern is deposited by thin-film deposition techniques that are amenable to photolithographic definition and etching to achieve much higher wirability than was possible for the thick- film approach. Thus, the thin-film conductor width and the spacing between them is typically 1 mil or less, and the via grid is on a 10-mil pitch; this is an order of magnitude finer than ordinary wiring boards. The resulting increased wirability makes it possible to interconnect even the most densely packed structures with only 2 (at most 4) interconnecting conductor layers, in addition to power and ground planes. Dielectric layers between these closely- spaced conductor runs must also be about 1 mil or less. To achieve this uniformly over a large substrate area and achieve planarization at the same time, thin (l-mil) polymeric dielectric layers are spun or sprayed on between the conductor layers. Polymeric films have the added advantage of a lower dielectric constant (2 to 4) that allows faster signal propagation. Silicon is often the substrate of choice ( inspite of its brittleness, low current-handling capability, and difficulty in making many connections), because of the TCE match it provides, its superb thermal conductivity, and its compatibility with silicon chip processing equipment already in place. Not only does this reduce investment requirements, but the reliability is also expected to improve with the application to packaging of the processes that have proved their integrity on the chip level. Packing densities as high as 90 percent are proj ected. Table 3-1 summarizes some

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47 recently reported high-performance, bare-chip interconnect technologies. specific example is shown in Figure 3-1, and additional MOM approaches are illustrated in Appendix F. TABLE 3-1 Emerging High-Performance Multichip Module Interconnect Technologies A Conductor Chip Module User Substrate W.T.P.* Insulator Attach** I/O** Advantages Disadvantages Mosaic1 Silicon Aluminum Silicon WB WB Vendor/Si chip High capacitance 11,2,22 dioxide Technology/TCE High resistance match lines IBM2 Alumina Copper Polyimide SB PGA Low attach Heat removal 8,6,25 inductance/ substrate for PWR/GND Honeywell3 Alumina Copper Polyimide WB/TB WB Substrate for 50,5,125 PWR/GMD AT&T4 Silicon Copper Polyimide . SB PGA Low attach Heat removal 10,5,20 inductance/ TCE match Silicon Aluminum Polyimide WB WB Vendor/TCE match - 40,5,100 Alumina Copper Polyimide Overlay WB No masks/fast Must remove 25,5,75 prototype/low overlay to attach inductance replace chips Silicon Various VariousBeveled Various Handle high pin Beveling step chip edge count/TCE match limited line routing MCC8 Alumina Copper Polyimide TB TB Programmable Silicon 15,6,50 interconnect HP9 Ceramic Copper Polyimide Augat10 Copper Copper Polyimide l (Rogers) Steel 100,25,250 1 NTTll Ceramic Copper Polyimide ~ No detailed data available 25,6,50 NTK12 Ceramic Multiple Polyimide ~ 25,5,65 J Mitsubishi13 Ceramic Copper Polyimide 50,5,100 References listed separately at end of table *W = width; T = thickness; P = pitch; conductor dimensions are in micrometers. Numbers are conservative reported values, not minimums.] **WB = Wire Bond; TB = TAB Bond; SB = Solder Bump; PGA = Pin Grid Array.

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48 References for Table 3-1: 1. H. Stopper, "A Wafer with Electrically Programmable Interconnects," Tech. Dig. IEEE Int'l Solid State Circuits Conf., p. 268, Fed. 1965. 2. C. S. Ho, D. A. Chance, C. H. Bajorek, R. A. Acosta, "Thin Film Module as a Hiah Performance Semi~nncl''~tr~r Package," IBM J. Res. Dev., vol. 26, p. 286, May 1982. 3. R. J. Hansen, J. P. Cummings, H. Vora, "Copper/Polyimide Materials System for High Performance Packaging," IEEE Tr. Comp., Hybrids, and Mfg. Technol., vol. CHMT-7~4), p. 384, Dec. 1984. 4. C. J. Bartlett, J. M. Segelken, N.A. Teneketges, "Multichip Packaging Design for VLSI-Based Systems," IEEE Tr. Comp., Hybrids, and Mfg. Technol. ibid., vol. CHMT-10~4], p. 647, Dec. 1987. 5. E. Bogatin, "Beyond Printed Wiring Board Densities: A New CoT'nercial Multichip Packaging Technology," Proc. Nepcon/East '87, p. 218, June 1987. 6. C. W. Eichelberger, R. J. WoJnarowksi, R. O. Carlson, L. M. Levinson, "HDI Interconnects for Electronic Packaging," SPIE Symp. Innovative Sci. ~ Technol., Paper 877-15, Jan., 1988. 7. D. W. Tuckerman, "Laser Patterned Interconnect for Thin-film Wafer Scale Circuits, IEEE Electron Dev. Let., vo1. EDL-8~11), p. 540, Nov. 1987. 8. S. Poon, J. T. Pan, T-C. Wang and B. Nelson, "High Density Multilevel Copper-Polyimide Interconnects," Proc. Nepcon West, p. 426, 1989. 9. C. C. Chao, K. D. Scholz, J. Leibovitz, M. L. Cobarruviaz, and C. C. Chang, "Multilayer Thin-Film Substrate for Multichip Packaging," Proceedings of the 38th Electronics Components Conference, pp. 276-281, 1988. 10. S. Lebow, "High Density/High Speed Multi-Chip Packaging," Proceedings of the 6th International Electronics Packaging Conference, pp. 417-423, 1986. . T. Ohsaki, T. Yasuda, S. Yamaguchi, and Taichi Kon, "A Fine-Line Multilayer Substrate with Photo-Sensitive Polyimide Dielectric and Electroless Copper Plated Conductors," Proceedings of the 3rd IEEE/CHMT International Electronics Manufacturing Technology Symposium, pp. 178-183, October 1987. 12. Technical Bulletin, NTK Advanced Product Group, "NTK High Density and Pligh Precision Wiring Ceramics," November 1988. 13. H. Takasago, M. Takada, K. Adachi, A. Endo, K. Ya~naha, T. Makita, E. Gofuku, and Y. Onishi, "Advanced Copper/Polyimide Hybrid Technology," Proceedings of the 36th Electronic Components Conference, pp. 481-487, 1986.

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49 H IGH DENSITY INTERCONNECTI NG TECHNOLOGY ROUTI NG SIGNAL POLYIMIDE IC CHIP LEVEL 1 DIELECTR 1C ROUTING SOLDER BUMP COD DING | LEVIEL 2 POWER CONNECTION POWER J AGROUND \ PLANE CONNECTION TH IN DIELECTRIC CAPACITOR GROUND PLANED DOPED SILICON WAFER FIGURE 3-1 Cross-sectional view of AT&T AVP module. For the highest frequency systems, MCMs represent a breakthrough in packaging. It is probable that this generic technology will come to dominate the packaging of components for the clockrate environment of higher than 100 MHz, with all present and intermediate future forms of circuit-board technology falling into disuse. Although there is already intense international activity in this area, further materials research, development, and application are strongly recommended. The interconnect issues, which all of these high-density approaches using bare chips must face, are listed in below. In many cases, line-density demands conflict with requirements on crosstalk, yield, ease of fabrication, ease of repair and circuit changes, and cooling difficulty. The systems designer must understand the trade-offs involved in committing a circuit design to a module layout and in working closely with the circuit designer to understand systems requirements such as chip placement and I/O layout to the next level of packaging. Testability of bare chips to operational speeds. Use of CAD for chip placement and optimum interconnect layout. Low inductance power leads (^I noise). Yield in interconnect fabrication (opens, shorts, vies). Transmission line impedance control.

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so Line resistance (DC and AC line losses, including dielectric loss and skin- effect losses in conductors ~ . Line capacitance to ground. Decoupling capacitors. Testability of interconnects. Testability of circuits to locate defective chips. Ease of change of interconnect routing. Repairability of interconnects. Reliability of interconnects under thermal and mechanical strain. Chip removal and replacement. Heat removal. Hermeticity, if required. Integrity of return current path. Wafer-Scale Integration Wafer-scale integration (WSI) implies an integrated circuit that, compared to state-of-the-art VLSI, has a quantum jump (not just incremental) in having more functions integrated on the same monolithic piece of silicon, much larger than a VLSI chip and normally of full wafer size. The attractiveness of WSI is in its promise of greatly reduced cost, high performance, higher level of integration, greatly increased reliability, and significant application potential. Among the advantages WSI promises are: lower cost per function because of a much higher level of integration and because of high yields made possible by fault tolerance higher performance because it leads to the highest possible packaging density of functions in a system and thus minimum interconnection lengths and signal delay. (This assumes that redundancy requirements will not negate the gains.) highest reliability because practically all interconnections in a system are by aluminum-metallization on silicon, which is inherently more reliable than other interconnection techniques, such as wire bonds or solder connections. (An additional dramatic increase in reliability can also be expected with the advent of self- reconfigurability, which makes possible failure tolerance, and transparency to systems operation.)

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51 dramatically higher functional density in both an evolving IC technology development environment, such as GaAs, and in a mature IC technology environment, such as silicon. significant application potential both for regular structures, such as memory, and for irregular structures, such as random logic. WSI cannot simply be looked on as a superchip that has larger dimensions than chips conventionally encountered in VLSI. The upper dimensions of a VLSI chip are normally determined by such factors as yield and defect density, allowable interconnection lengths (RC delay), or the dimension of available packages. For WSI, on the other hand, the most important characteristic is the requirement of massive testability and reconfigurability, referred to as fault tolerance. In other words, WSI greatly exceeds the ability to get a totally perfect circuit; that would be merely a large VLSI chip. Instead, WSI crosses into the arena of fault tolerance, with the attendant need for redundancy, constructability, and reconstructability. The committee exhibited considerable divergence of opinion in the preparation of thi s discussion in regard to WSI . Negative aspects perceived by some members include the following: The need for circuit redundancy in a planar configuration seriously impacts performance and packing density. Open metallization lines on a chip reduce yield. Redundancy requires increasing the number of wiring levels. Present management of semiconductor facilities, which strives to maximize the number of good circuits per wafer, is not optimally suited to NISI production. The majority of the committee concludes that WSI is unlikely to become an important interconnection strategy in the foreseeable future. PACKAGING MATERIALS REQUIREMENTS The required packaging improvements on all packaging levels are summarized in Tables 3-2 through 3-5 in the light of the VLSI chip technologies expected to be available in the future, as well as the future systems requirements. The latter include performance, electrical noise control, packaging density, reliability, and manufacturability.

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52 TABLE 3-2 Materials Requirements for Level 0 (On-Chip or Wafer Scale Integration) ~. . . . . System Drivers . . . . . . . .. . . .. . . _ VLSI Chip Or i vers ~- Large ch i ps or wafers 1 00-psec r i se and sett l ing times 1000 I /Os 256 s imu ltaneous ly swi tch i ng I /Os ~ i gh power dens i ty Performance Lower- temp . operas i on Lower ~ dielectric, low p conductors Multi layer s ~ gna l l ines E lectrical Noise Control Density __ Reliability Manufacturability Cross wafer communication, More functions per cm2 TCE compatibility Fault and failure d i st r i bused to substrate, to l erance power supplies keep small and matched Packag i ng Dens Sty Ground planes on wafers, impedance contra l H i gh ~ decaps on wafers, distributed power supp l i es on wafer - Superconduct i ng connect i ons No heat spreading on wafer 1.~-V power Low IR in Tight control Distributed power supplies power leads of L, C, R supplies on wafer, high ef f i c i ency, power by light 3-D construction Other EMI sens i t i v i ty = not applicable or data not available Shielded connector Damage contra 1 i n repair; fault isolation, on-chip repair and re- wiring, easy chip and wafer re- p lacement - Bu l letproof Low-res i stance passivation joints for direct . . 1ntrers 1 on coo l i ng Zero i nsert i on force connectors V i brat i on g-force in'T un i ty

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53 TABLE 3-3 Materials Requirements for Level 1 or 1.5 (Single-Chip or Multichip Modules) VLSI Chip Drivers Electrical Noise Packaging Performance Control Density Reliability Manufacturability Large die size - - High H. low Rid TCE compatibility Void control and inspect- of die and substrate, ability of die attach fatigue 100-psec rise High ~Distributed - Demountable 3-D - and settling conductors, power construction times low ~supplies (tight spacing) dielectrics, optical fibers 1000 I/Os 1 mil pitch, Staked vies Staked vies TCE compatibility Damage control in repair; 1:1 aspect solder control, outer ratio lead bonding materials for TAB, engineering change pad periphery, planarizability 256 - High ~ decaps High ~ decaps simultaneously closely switching I/Os located near chip High power Low IR drops - No heat If liquid cooling: density in signal and spreading corrosion, power lines possible charge transport 1.5-V power Low forward Tight R. L, C High-effi- - Low-resistance supply drops in control ciency power joining materials and power supply supplies, processes power by light 3-D Shielded - - Corrosivity of high Materials to resist construction vertical materials, radiation vibration, g-forces conductors hardness; hierarchy of sealing materials, adhesion, and purity control of plastics, outgassing, higher T s, nonhermetic enclosure Other - EMI, EMP radiation, upset radiation - = not applicable or data not available.

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54 TABLE 3-4 Materials Requirements for Level 2 (Modules on Printed Wiring Boards) System Drivers VLSI Chip Drivers Performance Large die size Flatness requ i remeet 100-psec rise and setti ng time 1000 I/Os 256 s imu ltaneous ly so i tch i no I /Os Low ~ boards, <13 mil hole s i zes, thi nner boards, I Sterna 1 v i as, Multi layer, 1 mi 1 pitch, mounting of . , p~n-gr~cs. High power Low IR drops - 1.5-V power supp ly 3-D construction Other E Centrical Noise Contro 1 Packaging DensitY ~li~hili~v - High H, Low R~ Impedance Distribution power control supplies optical fibers - Blind vies High ~ decaps High ~ decaps closely located near chip Heat spreading in 1st level package only, thermal vies, heat flow through board along board. High efficiency power supplies, power by light Low IR drops - ln power supplies T i ght board-to -boa rd spac 1 ngs - EM I, EMP red i at i on upset Manufacturabi 1 Sty TCE compati b i 1 i ty of package to board, fat i Due, barrel cracking If 1 iquid cool ing: - corrosion, board stability, charge transport Corrosivity of Cu board coatings. deterioration in sliding contact surface Demountable 3-D construction Solder control, damage control in repair, engineering change pad periphery, 10-mil lead pitch, lead fragility and control, lead solderability = not applicable or data not available

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ss TABLE 3-5 Materials Requirements for Level 3 and Higher (Backplanes, Cables, Connectors) __ SYstem Drivers VLSI Chip _rivers Large die size - 100-psec rise and settling time 1000 Ides - 256 simultaneously switching I/Os High power - density 1.5-V power - supply 3-D construction Other _ . . _ Performance Electrical Noise Control Optical fibers Impedance control Packaging Density __ Blind vies Lateral thermal conductivity, high- efficiency heat exchangers, plumbing, radiators Reliability Manufacturabil Sty TCE compatibility board to connectors, fatigue Reliable Remountable Tighter con contacts nector pitch, 3-D construc tions, de mountability If liquid cooling: -corrosion, -compatibility, -charge transport. = not applicable or data not available. Corrosion of Cu. protective coating, deterioration of Remountable contacts

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56 SUMMARY OF FUTURE PACKAGING MATERIALS AND PROCESSES NEEDS Future packaging needs are summarized below and include the following: ~ Fusible link materials with reversibility; Materials for fuses and antifuses; Multilevel interconnection processes on silicon; Thin and thick film magnetic materials for compact power supplies; Low-resistance contacts; Compatible power-device and digital-device processing; lIinority-carrier quality GaAs on silicon substrates; Inr~er lead capability down to a 2-mil pitch; High-yield, high-reliability metallurgical microjoining techniques; "Bullet-proof" chip coatings of "hermetic" quality; Corrosion resistance of chip and package materials toward liquid coolants OCR for page 41
57 Inspectable joint materials; Fine lead control; Quantum jump in connector reliability; Connectors with lead pitches down to 10 mils; "Smart" connectors and mixed optical and electrical connectors . Packages with windows transparent in certain wavelength ranges; Method of coupling to incoming light beams ; Shield conductors in Z-direction; J Laser processes for multilayer fabrication, Benign repair proces ses ; and Low- loss dielec~cri cs at high frequencies Greater than 1 GHz

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