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Chapter 4 MATERIALS ISSUES Materials science is an enabling technology that does not command interest for its own sake. Rather, materials issues play a key collaborative role in all matters of hardware design, fabrication' and performance. Thus, it is most effective to consider materials choices in the context of the physical design of specific packages and interconnection structures. In this chapter, relevant materials issues are discussed, emphasizing properties that are prime considerations in connection with the issues. It should be kept in mind that hardware is composed of combinations of materials, and the properties of the resulting complex are dominant in terms of performance. Materials compatibility is a critical issue, and interfaces count as much as bulk properties. Process compatibility is also a maj or issue. Each of the materials that enters a piece of hardware must be robust in subsequent fabrication steps. This involves exposure to process chemicals and process environments that may not be apparent in the design itself. The effects can be less than obvious. For example, cure state of a polymer or the grain structure of a conductor can be significantly affected by process conditions that are not intended to modify previously-formed structures. Stability in service is likewise an essential matter. Avoidance of corrosion, physical cracking, and other degradation or failure mechanisms is an important area of physical design in which materials properties play a central role. The issue of hermetic packaging is a materials-intensive one, and significant changes in practice and attitudes in this area can be expected over the coming years. Operating environment is a design factor best considered on a system level, but materials susceptibility to outside influence is often given too little emphasis. Design trends associated with increasing density of electronic circuitry include the following items: Power dissipation per unit area or volume is increasing. This effect is a consequence of miniaturization of the chips and the packaging and interconnection strategies that pack more devices onto interconnect structures. As more circuitry is placed on each chip, it is inevitable that packages must evolve with an increasing number of I/Os. Certainly, several hundred I/Os from single chips appears certain. As circuit elements become faster and faster, the speed of the package and its interconnect transmission comes to be a critical limiting factor. Today, the time required to move information from one chip to another is longer than the switching time of circuit elements on chips, a limitation that is growing in importance 59

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60 DISSIPATION OF HIGH THERMAL LOADS The increasing density of electronic packaging is accompanied by increasingly high thermal loads that must be dissipated. Heat dissipation is one of the most serious problems that limits the further miniaturization of electronic packages. High thermal conductivity in electrically insulating substrates is most relevant to solving the heat dissipation problem. Ceramics, dominantly alumina, are currently employed as substrates in high- thermal-load structures. Organic polymer dielectrics, as alternatives, soften and degrade at high temperatures. On the other hand, ceramics have higher dielectric constants than polymers, which has an adverse effect on propagation speeds. Moreover, ceramics are more difficult to form or shape than polymers, requiring processing at very high temperatures. One approach to combining the most attractive features of ceramics and polymers is to use ceramic particles or fibers as fillers in a polymer matrix to form a composite. In general, however, there is an empirical inverse relationship between thermal conductivity and dielectric constant of substrate materials, as shown in Figure 4-1; some typical values are given in Appendix E. This suggests that a physical design that separates heat flow paths from signal propagation media will provide the most effective strategy in regard to dielectric materials. Metals are better thermal conductors and can play an important role in thermal management. 10t 0 t~lAMOND EleO C) Al N O si O SAPPHIRE O O Si3 N4 A1203 E o 1 0- 1 _ ~ O CORDI ER ITE ' CSiO2 1 o-2 Sl LICON E (40% SiO2) (3 EPOXY `3 POLYIMIDE TRIAZENE 1 0-3 ~ O MYLAR OTEFLON .1,, ~ 1 1 1 I I I 1 1 1 _1 1 1 5 10 t5 do' Figure 4-1. Thermal conductivity-dielectric constant relationship of dielectric layer and encapsulation materials.

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61 The problem of thermal management, as it relates to the packaging of electronic devices, has been reviewed by Mahalingam (1985~. Generally, it is assumed that the junction temperature of integrated circuits must be kept below about 90C (this can vary from 60C to 120C depending on the application), and package, design, and heat transfer options are considered on this basis. Ability to remove heat depends critically on the type of package considered and on the commitment of the device to external cooling. For molded plastic packages (DIPs, Quads), thermal conductivity (as opposed to electrical conductivity) has been the principal driving force for the shift from alloy-42 lead frames to copper alloy lead frames. Heat flows out of these packages mainly along the metal lead frame, and copper is an order of magnitude more conductive than alloy-42. This improvement can also be achieved by introduction of a heat spreader, a metal plate such as aluminum, molded into the package. Packages of this type can handle up to about 2 watts with no external cooling and 3 watts in forced air. The very low thermal conductivity of the plastic makes attachment of a finned heat sink relatively unattractive. The silica filler used in epoxy encapsulants is also a poor thermal conductor (see the relevant section in Chapter 5~. Chip carriers and pin grid arrays have the chip in a cavity, and thus the thermal path through the die bond and encapsulation material is very important. Ceramic materials are chosen because of their superior thermal conductivty in comparison with plastics. The "cavity down" configuration is chosen to vent the heat away from the PUB. Roughly speaking, 3 watts can be handled without forced air and up to 6 watts with forced air if no heat sink is attached. With a heat sink and forced air, 6 to 12 watts can be accommodated with an alumina carrier. With beryllia packages, the power level can be increased by about a factor of two, i.e., to 20 to 25 watts. The quality of the die bond is important in these packages because the presence of any voids will cause a large thermal impedance in the main heat flow path. Very high power (greater than 1000 W) can be handled with structures mounted on a silicon substrate in which microchannels have been machined. Liquid is pumped through the channels as the heat-transfer medium. Kilowatt power levels may well be encountered in large, high-speed microprocessors. Values of specific thermal conductance of junction-to- ambient can be as low as 0.07 W/cm2/K for quite moderate junction temperature rises. The use of conventional liquid cooling is already established in mainframe computers. With intelligent engineering, such as is employed in table-top refrigerators, closed-circuit liquid cooling that uses microscope heat exchangers should be an attractive approach to thermal management for high-performance desk-top work stations. Polymeric circuit substrates are predominantly epoxies with glass reinforcement. Although the glass is introduced primarily to control thermal expansion, thermal conductivity also is improved. Continuous fibers work better than short fibers in all respects. Replacement of the glass with high- thermal-conductivity fibers (e.g., aluminum nitride) has been suggested but is very expensive. Research in this area could yield interesting composites. Metals are good thermal conductors compared to alumina, and their thermal conductivity can be enhanced further by incorporating continuous carbon fibers

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62 to form a metal-matrix composite. Because of the electrical conductivity of the metals, however, their use in substrates usually requires coating them with an electrical insulator, such as a ceramic or polymer film. For high- speed systems, the metal forms an essential reference plane. Coated metal substrates are valuable for applications that do not require operations that penetrate or degrade the dielectric (e.g., laser trimming). Heat sinks are essential aids in the dissipation of heat, although those currently used are bulky and not very effective. Materials with superior thermal conductivities are needed (e.g., carbon fibers in composites). Improved thermal contact is also needed between the sink and the part to be cooled, and thermally-conductive adhesives (metal-filled epoxies), greases, and other media have been used. It is important to keep the bond layer thin and avoid delamination. New designs emphasizing efficient heat transfer, small volume, and low weight are needed. Hermetic chip packages consist of ceramic bodies with external leads sealed through the ceramic. The chip is mounted in the ceramic body cavity and electrically connected, usually by wire bonds, then a metal lid completes the seal. To improve thermal conductivity, there is a need to find a metal more conductive than the currently used kovar. Metal-matrix composites (e.g., carbon, silicon carbide, or aluminum nitride in aluminum) are promising candidates for further development. Elkonite, an alloy of tungsten and copper (80:20) that has high thermal conductivity and TCE matching silicon and GaAs, is used in high-frequency digital packages. DIELECTRIC PROPERTIES Substrates support both active and passive devices and also the interconnecting conductors that make up the substantial subsystems or the entire system. Discrete components integrated into the substrate also may be involved. Signal transmission from one chip pad to a pad on another chip is governed by the dielectric properties of the substrate or interlayer and the electrical conductivty of the metal strip. If the total resistance is low, signals will be propagated with the speed of light, with a delay that is proportional to n = (\ Line termination is important to control reflections. If the resistance is large (greater than several ohms), transmission is slower and the effect of the dielectric constant exponent is even greater. Thus, the dielectric properties of the substrate play a crucial role in determining circuit speed. Detailed analysis of the transmission characteristics is highly specific to the geometry of the circuit. Dielectrics chosen for substrates generally have low dissipation factors, and only the real part of the dielectric constant is important. Surface conduction and electrochemical reactions can constitute ~ circuit failure mechanism, particularly in high-humidity environments, and, as circuit lines are miniaturized, this problem becomes more important. Dielectric breakdown normally is not a problem in interconnections. In printed circuit boards, hybrid circuits, and multichip modules, strip lines of various description occur. For example, in a multilayer board, a metal trace may have the substrate dielectric on one side and air on the other

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63 side, or a buried trace may have a dielectric on both sides. Adjacent power, ground, and signal lines have complex implications for impedance and crosstalk. In general, an intuitive average dielectric constant can be invoked to approximate the strip line characteristics. Substrates fall into two classes, inorganic and organic, with ceramics (mainly alumina) dominant in the former and polymers (mainly epoxies) dominant in the latter. Alumina has a dielectric constant of about 9, and epoxy-based composites have dielectric constants in the range from 3 to 5. Thus, the speed of signal propagation on polymer boards is considerably faster than on ceramic. Although both classes have materials that offer lower-dielectric- constant substrate materials, polymers are more promising in this characteristic. Multichip modules are designed to make use of the best of both. Beryllia (BeO) has been mentioned as an alternative to alumina (A12O3), but mainly in the context of its thermal conductivity rather than its dielectric constant (E ~ 6.71. Beryllia is toxic and requires special precautions during processing. It must be fired at high temperatures, a requirement that is inconsistent with co-firing with copper. Aluminum nitride (A1N) is another alternative to alumina, but it offers no advantage in dielectric constant (E ~ 8.9~. Glass-ceramic compositions based on cordierite have i' between 5 and 6 and have the possibility of copper co- firing compatibility. This promising area is now receiving development emphasis. Foamed ceramics offer even lower i', although they suffer in terms of mechanical strength and thermal conductivity. Even so, foamed ceramics deserve exploration. New epoxy resins based on more highly functionalized materials now are being introduced for high-performance circuits when their dielectric constant is not the driving property. In view of the sophisticated (supercomputer) systems recently introduced based on epoxy boards, it must be concluded that epoxy resins in multilayer boards will remain dominant for the foreseeable future. Very advanced structures have been demonstrated (i.e., fine lines and many layers>, and the processes employed are familiar. Other polymers with lower dielectric constant are available but are less well accepted. Many polyimides of varying chemical composition have been studied. In general, the polyimides have dielectric constants in the range of 3 to 4, but this varies considerably with humidity. High frequency dielectric loss is a negative factor in dielectrics that absorb water. Fluorinated resins have lower dielectric constants, as low as 2 for polytetrafluoroethylene. Cyanate (E'about 2.8) and benzocyclobutane (BCB) resins (E' about 2.7) lie in between those mentioned. An interesting cyanate resin-polytetrafluoroethylene fiber composite has been made available in sample quantities (E'about 2.6), but the price is prohibitive at this time for general use. The search for low- dielectric-constant materials continues among a variety of candidates, but a great deal of development work is needed. Materials with high dielectric constants at high frequencies are necessary for power-supply decoupling. Their incorporation in substrates would be a worthwhile direction for the future.

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64 INTERCONNECT VOIDING The reliability of interconnections on integrated circuits on chips is degraded often by the process of electromigration. In this phenomenon, small circuit traces develop cracks or voids when carrying high currents for substantial periods. Although this phenomenon is not completely understood, empirical studies have led to design rules for selection of alloys that minimize the problem. As interconnection traces on multichip modules are further mir~aturized, electromigration may again cause problems. A separate, but closely related, problem involves conductor voiding, which is driven by mechanical stresses in the metal. This phenomenon is less well characterized than electromigration and could become a design problem at module-conductor dimensions; it is most likely to occur in low-melting, ductile materials, e.g , PhIn. The-com~ittee could identify no example of voiding problems of this nature in interconnect structures, as yet. THERMAL FATIGUE Interconnect structures are complex assemblies of various materials separated by interfaces. Adhesion varies widely in going from one layer to another, and the coefficient of thermal expansion differs from one material to the next. As a consequence of these differences, stresses are generated as the temperature is changed, and the stress will be proportional to the physical size of the interface and to the temperature difference from some state of low stress. Thus, a silicon chip with an attached metal alloy lead frame which is transfer-molded in a silica-filled epoxy, will develop stresses as the assembly is cooled from the molding temperature to room temperature. In some cases, the stresses can be sustained by the material system, but in other cases the stresses cause the package to warp, twist, or deform. Finally, the package may fail completely by the cracking of the chip or the encapsulant or by delamination of the interfaces. Temperature cycling, employed in device testing, exercises the structure repeatedly and increases the probability of mechanical failure. Compliant layers can decrease thermal stress. Also, TCE matching can be approached through use of composite materials. Designers must, therefore, have extensive knowledge of materials properties arid the nature of interfaces to ensure stable arid reliable interconnection structures and packages. The analysis of actual structures is exceedingly complex, even in relatively slap] e systems, and much design lore and structural approximation are employed. Intuition is often faulty in this area; for example, thermal fatigue of soldered j oints is complicated by solder creep . INTERFACIAL PROCESSES Adhes ion and bonding are required at virtually all interfaces within an interconnect structure. Stresses -in the structures are mitigated when they are distributed over well- adhered surfaces, but delamination results from

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65 stress concentrations that can cause fracture, which allows subsequent rapid moisture ingress. An understanding of the fundamentals of adhesion among the common packaging materials is clearly incomplete. Although adhesion is well controlled and optimized in most present designs, there are still many cases where adhesive failures occur. As new materials are introduced, each new interface will need detailed study for adhesive reliability. Although computer design aids and greater understanding of adhesion will improve design effectiveness, it is doubtful whether new materials or processes can be introduced without an extensive testing program. As an example, epoxies bond well to many different surfaces, but moisture ingress, poor design, or surface changes can weaken its adhesive strength. Hydrocarbon and fluorocarbon polymers, on the other hand, are inherently difficult to bond. Polyimides have been adapted to meet interconnect requirements, and new adhesive forms are available. Interdiffusion processes are of less concern for interconnects than they are for chips, but other long-term phenomena, such as physical aging and migration of additives to the interface, are still of concern. Lower-temperature processing will be of some help, but the higher operating temperatures of high-power devices will exacerbate these phenomena. HIGH-TEMPERA1~E STABILITY AND CHEMICAL REACTIONS Interconnection and packaging materials are tested at temperatures ranging from -40 to +150C; temperatures experienced in use are usually well within this test range. However, fabrication process temperatures can reach 350C. Ceramics are exceptionally stable in this context. Most metals do not pose problems, but solder creep is a special issue. This may be addressed by the development of creep-resistant composite solders or solderless connections involving directionally conductive composites. Nevertheless, it seems safe to predict that solder will remain the dominant electrical joining material for the foreseeable future. Epoxies also are well behaved if formulated and cured correctly, but epoxies deteriorate in time. Other polymeric materials may deteriorate with time as a result of oxidation, hydrolysis, and photochemical effects, although this is not usually a major issue in packaging. Polyimides are a special problem when produced as solvent-cast dielectric layers. The polymer is soluble only in the polyam~c acid form and must be thermally cured to the polyimide after casting. It is important that the copper be protected from the polyamic acid during curing (e.g., with the use of chromium). TRACE RADIONUCLIDES IN PACKAGING MATERIALS The importance of radiation-induced upsets (charged with particles entering and affecting the crystal structure) in microelectronic devices has become increasingly important as memory size has diminished. Some commercially-available dynamic RAM s function with about 10 million charge carriers per bit, or about 1 picocoulomb of charge. An alpha-particle (He) incident in this region of a memory may create a sufficient number of local carriers to disrupt bit storage at that level. This effect was first observed about a decade ago and has been the subject of several investigations. It has

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66 been found that very low levels of uranium and thorium can create such upsets, and it is recognized that essentially all materials contain these elements at part-per-billion levels. The problem can be particularly significant with some materials; e . g., alumina typically contains uranium at levels of about 100 ppb and requires the shielding of the active chip surface. Fortunately, alpha particles have a very short propagation range in dense matter. Silica filler used in plastic-molded packages is also an obvious source of alpha emission close to the chip surface. Suppliers have solved this problem by developing a low radionuclide silica, now synthetically produced. Cosmic rays also can give rise to the same problem, but, in this case, there is no way to shield the memory circuit. Thus, it is necessary to resort to circuitry solutions involving error-correction techniques. ELECTROMAGNETIC INTERFERENCE Along with the increasing sensitivity and abundance of electronics is the increasing severity of electronic pollution. The shield for electromagnetic interference (EMI) is necessary for connectors, cables, chassis, cases, etc. Metals, particularly aluminum, are most widely used for EMI shielding. They can be in the form of sheets, coatings, etc.; however, metals are not easy to shape compared to polymers and are relatively heavy. Moreover, coatings can be scratched and hence can degrade their shielding effectiveness. Polymer-matrix composites containing electrically-conductive fillers (e.g., graphite) are moldable and can be comparable or even better than metals in their EMI shielding effectiveness, particularly at high frequencies. More work is needed in the development of such polymer-matrix composites. High-temperature superconductors are potentially valuable for EMI shielding, although the need to cool to below the critical temperature (Tc) limits their usefulness. Nevertheless, superconductors may have unusual shielding capabilities and deserve attention. ENCAPSULANTS AND HERMETICITY Hermetic packages are intended to provide complete protection for the integrated circuit chip from all external influences. In practice, this usually implies the exclusion of all forms of water from the active silicon chip and its lead frame. In fact, chips are passivated by a thin glass layer (usually Si3N4), but an external, robust package is required for high- reliability applications. Suitably prepared ceramics and metals are impermeable to gases and can produce effective hermetic packages. Typically, the chip is bonded inside a ceramic body cavity, and a lid (metal or ceramic) is attached with a glass or metal seal. Ceramic-to-metal seals that can withstand thermal cycling are needed. All polymers are permeable to gases and thus are unsuitable for hermetic packaging components. Hermetic packages are expensive and involve lead impedances that make substitution options a matter of considerable interest. There is further concern that many so-called hermetic packages are in fact leaky. One

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67 alternative is the use of silicone coatings that passivate the active silicon surface. These materials are permeable to water vapor, but they preclude the formation of liquid water on the inner surface and thus eliminate corrosion reactions. At present, these material coatings have not been accepted as substitutes for hermetic packages, but extensive test programs are being actively pursued to provide data that could justify substitution. There are strong and highly divergent opinions on this issue that are unlikely to be completely resolved across the board in the near future. (See the section on "Military Packaging'' later in this chapter.) lIATERIALS-RELATED RELIABILITY ISSUES Packaging and interconnection reliability issues are usually related to materials chemistry failure mechanisms. As circuit density increases, many of these mechanisms will be exacerbated. The focus in this type of failure mechanism is on combinations of materials--e."., corrosion by galvanic couples, stress concentrations from thermal expansion mismatches, and loss of interracial adhesion. Environmental factors in service usually center on water penetration, particularly when salts are present. Exposure to solvents, wide temperature excursions, mechanical shock or defog ovation, and particulate contamination also are significant. Assembly processes (e . g., solder reflow for surface-mount devices) can subject packages and interconnections to more severe conditions than those encountered in product use. Corrosion is a persistent threat that is minimized by eliminating ionic impurities from the materials. Epoxy molding compounds were once a major source of chloride contamination, but resin suppliers have significantly reduced the problem. Soldering operations involving fluxing can cause impurity entrapment that often leads to long-term corrosion and eventual circuit failure. The presence of ionic impurities with clustered water is particularly serious, since they form an electrochemical cell that rapidly accelerates corrosion. Conditions conducive to water clustering, such as voids or delaminated interfaces, must be prevented. This once again indicates the importance of interfacial adhesion in promoting device reliability. Corrosion is a widely occurring phenomenon that affects most metals. Specifically, the copper commonly employed in lead frames, printed circuit boards, connectors, wire, and cable is subject to corrosion. In general, liquid water must be avoided. This is more difficult than it may seem because of the common presence of salts, and it will begin to condense at about 70 percent RH when salt contaminants are present. Thus, it is necessary to clean all parts careful ly and prevent subsequent contamination . Gold may be used for very high-reliabi~ity circuits. Silver is employed in some cases, but sulfiding and migration are problems . There is no very effective method to test for corrosive agents, and accelerated thermal aging does not suffice. Interfaces with imperfect adhesion often become the sites for concentration of corrosive action (e.g., on the glass reinforcement in epoxy multilayer boards). Metal connections in some cases can interdiffuse and form brittle intermetallic compounds (e.g., aluminum and gold), and this continues to be an

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68 important problem in packaging and interconnection (Herman and Wilson, 1989 ~ . It is extremely important to form good bonds in component manufacture and assembly, and a great deal of engineering knowledge has been amassed in this area. As wire bonding becomes inadequate for high I/O chips, this area will be a central issue for an alternative technology. TAB is an alternative candidate that has been available for many years, but there still are s ignificant remaining questions in regard to effective chip bonding. Even now, the future of TAB is uncertain. Wire bonding, nevertheless, could continue to be important for several years. MILITARY PACKAGING The military environment is one that puts great emphasis on packaging technology. There is a requirement for operation and survival in extreme conditions of high and low temperatures, high humidity, temperature cycling, etc., all of which are identified in military specifications to which military electronic packaging must be qualified (e.g., MIL STD 38510 group D tests on individual device packages). More generally, there are requirements for conformance to package outlines and packaging materials within the framework of denser packaging (more gates per cubic inch) and lighter packaging (more gates per pound). As a result of extensive tests of transistors in a variety of package types evaluated for survival in high-moisture ambients dating back to the 1950s, most military systems include a requirement for hermetic packaging. Every package incorporates a cavity around the active chip, and that cavity is tested for leaks to the outside environment. Ceramic and metal packages meet that requirement and have been used in military systems, to the exclusion of plastic packages, for the past 30 years. Because of the desire for maximum packaging density, there is a tendency to use flat packs rather than dual- incline packaging. Similarly, in recent years, when the push for closer lead spacing and higher lead counts has put pressure on military packaging, leaded and leadless chip carriers, surface- mounted to high-density printed circuit boards and to ceramic modules, have become dominant in military systems. Such packages permit lead counts up to 400 and lead spacings down to 20 mils. Indeed, such high-density modules have been standardized under the Standard Electronic Module (SEM) title in sizes from 2 by 5 in. to 5 in. by 5 in. Multiple ceramic modules are then mounted on larger printed circuit boards as required. The modules are partitioned to permit module pin counts only slightly higher than individual device pin counts. Military system designers are increasingly concerned with the penalty paid by adhering to requirements for hermeticity, and activities are under way (specifically by the Air Force Wright R&D Center, Attn: S . E. Wagner) to provide assurance that polymer-based systems can be used without any significant reliability impact as they are being used in commercial and industrial systems (Won" 1988~. Such systems involve barriers to contaminants on the chips and strong bonding of the polymer to the chip surface, so that motion by mobile ions in surface moisture layers is impossible. The

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69 acceptance of such systems will result in substantially higher density, since the sealing structure uses a great deal of surface area. Simultaneously shifting to chip-type lithographic techniques will permit multilevel interconnect layers under or over multiple chips on a single substrate, so that the chips can be placed almost butting each other. The replacement of wire bonds by techniques that apply many bonds simultaneously beg., tape automated bonding, flip chips, or other techniques) will permit significant improvements in module reliability, since the wire bonds are still a relatively fragile interconnection methodology. One of the areas of greatest importance in the packaging hierarchy is the power supply. Military systems generate and distribute power at 20 to 50 volts. Locally, there are power converters that convert the power to the 5- volt level that is most usually required by chip circuitry. Recently, the faster switching parts and the tendency for many gates and drivers to switch simultaneously has resulted In a desire to do power conditioning at the second package level and to use decoupling capacitors to further stabilize the supply voltage at the chip terminals. Small, lightweight, high-frequency switching supplies are responsive to this requirement, and they are appearing in new military systems. The ability to cool such distributed power converters is an important aspect of modern military system packaging structure design. REFERENCES Harman, G. G., and C. L. Wilson. 1989. Materials problems affecting reliability and yield in LSI devices. Materials Research Society Proc., vol. 154, p. 401. Mahalingam, M. 1985. Thermal management in semiconductor device packaging. Proc. of the Institute of Electrical and Electronics Engineers, vol. 73, p. 1396. Wong, C. P. 1988. Electronic packaging materials science II. Materials Research Society Proc., vol. 108, p. 175.

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