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Chapter 5
SOME SPECIFIC MATERIALS
In this chapter, several specific materials or classes are described.
These examples will give a flavor of the complex compromises that must be made
in optimizing material and process choices . Even so, the presentation is
simplified, and it should be emphasized that materials engineering for
packaging and interconnection follows requirements set by system design
considerations. Thus, at any given time, system needs may put pressure on a
specific property. Cost, in general, is a critical issue, although it is not
susceptible to treatment in a report of this type. Cost is both volume- and
process-dependent, further complicating the material design choice.
THE EVOLUTION OF EPOXY MATERIALS IN PLASTIC PACKAGING
\7arious epoxies have been developed in recent years, and today they play
an important role in electronic packaging. The following sections cover some
of the special features and how they can be modified to meet specific needs.
Epoxy Versus Silicone Materials
The earliest materials used for plastic packaging of microelectronic
devices were silicones because of their high-temperature performance and high
purity. The common bisphenol-A (BPA) epoxies were introduced that have lower
glass transition temperatures (T~) . Novolac epoxies are generally preferred
over BPA materials because of their higher functionality and attendant
improvements in heat re s i s Lance Howeve r, epoxie s can have high ionic
impurity levels because their reactior~ chemistry uses an excess of halogen-
containing epichlorohydrin. Hybrid encapsulant materials consisting of
epoxies and silicones captured a large segment of the molding compound market
in the mid- 1970s because they combined some of the high- temperature
performance and the high purity of the si li cones witch the mechanical
properties and the solvers yes istanc~ of the epoxies . Molding compounds s ince
then have moored steadily toward all - epoxy systems ~ as the high- temperature
novolac materials were improved and the ionic impurity levels were driven
below 100 ppm. Figure 5-1 charts the property and process evolution.
71
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72
1 970
1 980
1 990
DRAM
LOGIC (# GATES)(CMOS)
1 6K 64K 256K 1 M 4M
0.1K 1K 10K 100K
l | FLAME RETARDED3
l | LOW IONIZ} BLE CHLORINEl
| LOW STRESS
I | LOW a- EMISSIONl
,
ANi1YDRIDE CURE f
r
I AMINE CURE NOVOLAC
a. ~
STRESS MODIFICATION
.
rSYNTHETIC SiO2 flLLER
THERMAL STRESS (MPa)
THERMAL EXPANSION(x10~6/°K)
IONIZABLE CHLORINE (ppm}
UlTh CONTENT (ppb)
FLAME RETARDANCY
CURE TIME (SECONDS)
MELT VISCOSITY (POISE) (MIN.)
MOISTURE SENSITIVITY (REL.)
TEMPERATURE CYCLING (REL.)
12
1 10
1 00 500
Figure 5-1. Property improvement history of epoxy encapsulating compounds,
1970-1990.
Low-Stress Materials
A major advance in epoxy molding compounds was the development of the
low-stress materials in the early 1980s. Package cracking, passivation-layer
cracking, and circuit-pattern deformation can all result from the disparities
in the coefficients of thermal expansion among chip, plastic package, and
metal leadframe. This problem was exacerbated as the surface area of memory
devices with 64K and 256K DRAMs became a significant fraction of the package
itself. The plastic edge thickness became thin, and cracking began to Occur.
To alleviate this problem, the low-stress molding compounds combined several
,, ~ alstr1 outlons were used to
increase the filler loading to over 72 percent by weight, thereby reducing the
coefficient of thermal expansion by as much as 25 percent (21 x 10-5 to
16 x 10-5 in./in.°C). The second advance was the addition of elastomeric
modifiers in a dispersed domain morphology, which improves toughness.
Research on the size, size distribution, and interracial region was a
contributor to the improved performance of these materials. It is at
point that the Japanese suppliers surpassed the domestic suppliers in
compound performar~ce.
approaches. Fillers we to rent size and snare
The s econd advance war the
major
this
molding
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73
Low-Alpha Materials
Alpha particles emitted from the silica fillers can cause soft errors in
memory devices. The development of molding compounds that were low-alpha-
particle emitters was ~ major advancement. Although these materials were
available from the late 1970s, the silica was from the few mines that had low
natural uranium and thorium contamination. Supplies were scarce, and prices
were much higher than conventional materials ($25/lb compared to $3.50/lb).
The use of synthetic silica in the early 1980s reduced the price of low-alpha
materials to $10/lb by 1986. These materials quickly captured the market for
memory devices? effectively eliminating silicone rubber in applications where
it was used for alpha-particle protection.
Processing Improvements
Processing improvements also were required to keep pace with the
increasing demands of higher-pin-count packages. The 40-pin DIP of the early
1980s was the first design to experience significant flow-induced stress
problems. The long cantilever of the leads and the close proximity of the
wire bonds made the package much more susceptible to lead movement, paddle
shift, and wire sweep; the forces are proportional to the product of the
material viscosity and its velocity. Japanese suppliers led the way in
developing materials that had significantly lower viscosities than the
previous generation of materials. The introduction of fine-pitch packages and
thin leadframes has continued to push the need for very-low-viscosity molding
compounds. The viscosity at the molding
temperature has been reduced from 1500 poise in 1980 to 300 poise (at 100 sect)
in 1988, while both the filler loading and crack resistance of the material
have been increased. It is also significant that the cure time for epoxy
molding compounds has been reduced from 3 to 4 minutes in the mid- 1970s to 60
to 90 seconds in the late 1980s, thereby contributing an important
productivity increase.
Market Shares of the Maj or Molding Compound Suppliers
Japanese firms now hold 70 percent of the world market share in epoxy
molding compounds for IC packaging. Less than a decade ago, U. S . companies
had the maj ority of the market. This substantial U. S . market share advantage
waned with the introduction of newer low-stress epoxy novolac materials. High
purity, low viscosity, and low shrinkage stress were the major technology
areas where the domestic suppliers fell behind.
FUTURE TRENDS IN PLASTIC PACKAGING MATERIALS
Advancements are needed to meet the challenge of future high-density
packaging requirements. Some of these are discussed in the following
sections.
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74
Surface-Mount Technology
Surface-mount attachment of IC packages will grow very rapidly over the
next five years. The use of vapor phase and IR reflow solder methods for
surface-mount devices exposes the entire molded body to high temperatures that
can cause cracking through two different mechanisms. The first is by the
thermal shrinkage forces already discussed. Continued reduction in the
coefficient of thermal expansion, reduction of the glassy modulus, and
additional improvements in adhesion will be needed to prevent thermal-
shrinkage stress cracking of the molded body.
The second crack mechanism is through rapid vaporization of moisture
within the molded body, which causes volume expansion above the glass
transition temperature (T~) of the plastic package. To alleviate this serious
problem, there are four possible material improvements that could be made: a)
lower the moisture uptake of the molding compound, b) increase the Tg to near
the solder reflow temperature, c) increase the mechanical modulus above Tg to
minimize high- temperature deformation, and d) improve adhesion to the bottom
surface of the paddle, where delamination occurs.
Very High Pin Count Packages
Pin counts for microprocessors and logic gate arrays will continue to
rise rapidly over the next several years. This will cause package dimensions
to grow significantly despite the anticipated reductions in lead spacing.
This trend will continue to put pressure on the processability of epoxy
molding compounds. Larger packages with thin lead frames and very narrow
spacings between the leads and wire bonds are much more susceptible to flow-
induced stresses. Continued decreases in molding compound viscosity will be
needed to package the 196- and 244-pin packages that will appear in the next
few years, since current materials and processes may not be able to realize
high production yields on these designs. New process technology, such as the
multiplunger transfer molding and smaller conventional molds, may be required
to provide the long cavity fill times needed to reduce the flow-induced
stresses, if further viscosity reductions cannot be achieved. Pin and pad
grid arrays (PGAs) could show substantial volume growth if the lower
productivity of molded high-pin-count packages increases their costs close to
that of the PGAs ; the PGAs generally are easier to assemble onto printed
wiring boards than fine-pitch chip carriers that are restricted to edge leads.
Heat Dissipation
Power dissipation requirements of IC devices have been steadily rising.
Although the shift from ECL to CMOS technology has at present substantially
reduced the problem, it is only a postponement. Power increases rapidly
because power dissipation scales linearly with feature size at constant
voltage, but on-chip circuit density increases as the square of the feature-
size reduction ratio. Continued growth in device integration and
miniaturization will push the power per chip to over 5 W in the near future, a
level that cannot be easily dissipated in a conventional plastic package
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design. Thermal management will become much more important than it is at
present, and the epoxy molding compound will have to play a major role in this
management if the costs of plastic packages are to remain low. High-
conductivity fillers are available, such as alumina, silicon nitride, silicon
carbide , and magnesium oxide ~ see Appendix E) . These alternative materials
are all very abrasive. Developments in tool design may enable manufacturers
to use these more abrasive materials, or surface treatments for the fillers
could be developed to reduce their abrasiveness. The dielectric properties of
these alternative fillers are not as good as silica (see Appendix E). In the
absence of these technical developments, active thermal-management components
will have to be added to the packaging. Devices such as molded-in heat
spreaders or added-on cooling fins could significantly affect package
manufacture and assembly, however, with attendant increases in cost.
Figure 5-1 recounts the improvements in thermoses molding compounds
since the 1970s, and the expected needs over the next few years.
Plastic Alternatives to Epoxy Encapsulation
Plastic encapsulation of integrated circuit chips is, as noted above,
dominated by novolac-based epoxies that are heavily filled with silica powder.
These compounds are ther~osetting (i.e., the resulting polymer is highly
cross-linked) and the transfer molding cycle times for processing are long
compared winch injection-molding cycle times . On the other hand, transfer
molds typically have hundreds of cavities producing hundreds of parts per
cycle. The viscosity of a thermosetting epoxy evolves in a complicated
manner, and thermoplastic compounds could well prove eas ier to process .
However, procedures for processing epoxies are widely practiced, and the
technology is entrenched. Reuse of scrap, as an economy, is another reason
for considering thermoplastic encapsulants.
Liquid crystalline polymers form another class of material that is under
cons iteration as a replacement for epoxy encapsulants. These materials are
usually aromatic polyesters that contain naphthalene groups in the main chain.
They form anisotropic liquids and solutions, and molded parts retain the
anisotropic properties, an aspect that may be turned to advantage in a well-
designed process because excellent mechanical properties can be achieved.
This area is worthy of further research and engineering support to investigate
the potential of liquid crystalline polymers in electronic packaging.
Polyphenylene sulfide is a thermoplastic material that has been
available for several years as an alternative to epoxies. No widespread use
has been reported, but development continues. This material can produce
corrosive acid by-products and must be compounded carefully to avoid problems
that could arise. As with epoxies, polyphenylene sulfide is filled with an
inorganic powder, usually silica, to reduce the TOE.
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76
ORGANIC PRINTED CIRCUIT BOARD MATERIALS
Printed circuit substrates for electronic systems are usually organic,
although circuits in the high-performance area tend to have more ceramic-
based representation. It is obvious from Figure 1- 8, discussed in Chapter 1,
that chip technology in terms of density has advanced much faster than circuit
board technology, conductor width and other features on ICs were 10 times
smaller than those on circuit boards in 1965, and today they are about 100
times smaller. This linear gain is even more important in terms of circuit
area. Progress in interconnection has not been as great. The large mismatch
in dimensions that has now developed, less than 1 Am on the chip to more than
100 ,um circuit boards, will over the next few years almost certainly lead deco
more extensive use of circuits of intermediate density.
The dominant material for circui t boards for more than two decades is a
glass - fabric - reinforced epoxy res in labeled FR-4 . This material is fire -
retardant, stable, and amenable to high-volume processing. Inner layers in
MLBs are available as B-stage material that can be processed to generate
circuit traces and vies, then "layered up" and pressure-cured into the final,
coordinated multilayer structure. This system has served the industry well
and is likely to continue in widespread use for circuits that do not contain
features smaller than about 100 Am (4 mils ~ .
Advanced circuits appear to be moving to an improved version of FR-4 in
which the bisphenol-A epoxy is replaced by a more highly crosslinked resin
(novolac), a resin related to the molding compound employed for chip
encapsulation. The glass reinforcement may also be modified or replaced to
meet circuit demands. Thus, with only minor modification, it can be predicted
that FR-4 will provide excellent circuits with features of about 20 Am in
size. This development should provide MLBs of considerable sophistication for
the remainder of this century. The availability of this improved FR-4 will
blur the boundaries between very-high-performance circuit boards and multichip
modules.
Other organic materials have coexisted with FR-4. FR-2 is a paper-
reinforced phenolic resin, an inexpensive substrate material for single- and
double-sided circuits. This substrate is popular in Japan. Molded printed
circuits have been manufactured mainly from polyether sulfone and polyether
imide. Several forms of flexible circuitry exist, including polyimide film,
polyester film, and glass-mat--reinforced polyester. Japanese consumer
products employ polyimide film circuits. The glass-mat polyester also was
used in telecommunications equipment. These materials (FR-2, flexible
substrates, and some other examples) were (or are) niche products that are not
part of the high-density substrate evolution history.
Beyond the improved FR-4, there are a number of alternative substrate
and dielectric polymers available to meet specific needs. Polyimides provide
excellent high- temperature performances, and a great deal of engineering has
been conducted on this class of materials. Bismaleimide-triazene polymers (BT
resins) exhibit good high-temperature properties and are compatible with
epoxies. Polytetrafluoroethylene and certain highly crosslinked hydrocarbons
offer a low dielectric constant as well as high-temperature performance. As
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77
the need arises for employing these more advanced materials, sources with the
requisite expertise are available in the United States as well as in Japan.
It remains to be seen which country will take the lead in producing materials
and processes in this area.
PROCESSING TECHNOLOGY FOR CERAMIC PACKAGES, BOARDS, AND SUBSTRATES
The earliest packages for electronic circuitry were metal packages, and
the interconnection between devices was generally done with wires. The
earliest use of ceramics came in the form of bases for electron tubes with
glass-sealed electrical feed-throughs. With the demand for miniaturization,
some circuit designs began to use ceramic substrates. These provided a strong
board upon which various wiring patterns could be placed. During the 1950s,
the technology was developed for interconnecting various discrete devices
using metal lines on these substrates. Furthermore, the technology for
placing some resistors on these substrates in the form of thick films was also
introduced.
One of the first applications of the ceramic package came with the need
to house a simple quartz oscillator. This also was done in the late 1950s.
While the substrate technology had led to miniaturization of resistors and
capacitors, the individual transistor devices were still packaged in metal
cans with the typical 3 lead wires protruding from the bottom of the can.
This design was inconsistent with a low profile, so the model of the package
used for the quartz oscillator acted as the driver for the first ceramic
bans is tor package .
With the use of a ceramic substrate technology for interconnections, it
quickly became obvious that, with increased complexity of circuitry, it was
necessary to have a means of permitting one conductor path to cross another.
A number of schemes were developed to do this, using complex insulated
crossovers and small bridges, but the real technology for handling this
problem came in two forms. These two forms, the ceramic multilayer tape
process and the screen-printing process, constitute the basis for much of
today's processing technology for ceramic packaging. Discussed in the
following sections are some of the earliest technologies for making ceramic
parts as well as the two major current processing technologies mentioned
above.
Dry Pressing
The earliest process for making ceramic parts for electronic circuitry
was that of dry pressing, and this included the substrates used for
interconnection. In this technology, the powder is usually prepared by mixing
the raw materials as a slurry in a ball mill. The material is dried and then
calcined for phase formation and intial chemical reaction. The calcined
mixture is again ball-milled to grind it into very fine particles, and this
ground powder is then dried to prepare it for pressing. In the pressing
operation, the powder is typically poured into a cavity of a metal die, and
then the die plunger presses the powder into the desired shape. This
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technology can be cumbersome and relatively expensive, does not lend itself to
having any buried conductor paths, and gives a part with a limited surface
smoothness.
The Ceramic Tape Process
The ceramic tape- casting process Sometimes known as the doctor-blade
process ~ was adapted from a process typically used in fabricating sheets of
polymers or organics. In the ceramic adaptation, ache powder is mixed with a
liquid solvent containing various organic additives, which act as binders,
dispersants, and plasticizers, to give a slurry with a viscosity roughly that
of heavy cream. This slurry is poured into a reservoir and then spread into a
thin sheet by having the slurry pass under the gate, known as the doctor
blade, as either the reservoir is moved over a smooth sheet, or a smooth sheet
is moved under the reservoir. After casting, the slurry is allowed to dry by
volatilization of the solvent. The dried ceramic still contains sufficient
organic binders so that the tape can be stripped from the carrier, and it
exhibits sufficient flexibility and strength to be handled, cut, or punched.
At this stage, the tape is referred to as a "green" tape, meaning an
unsintered ceramic tape. The thickness is generally in the range of 0.5 to 1
mm .
This ''green" tape can be used to fabricate substrates by punching the
substrate shape from the rolled green tape, heating the piece to temperatures
of about 200 to 300°C to pyrolyze or volatilize the organic binders, and
finally heating to a sufficiently high temperature to sinter the ceramic
particles into a dense, hard sheet. Because the particles are well dispersed
in the original slurry and because the surface of the tape is very smooth, the
sintered ceramic offers a high-quality, dense, pore-free, strong surface on
which to place electronic interconnect devices.
By about 1960, the concept of making a multilayer substrate or ceramic
package was introduced. In this technology, some or all of the metal
interconnect lines are buried within the final ceramic. This is accomplished
by printing the metal lines on each of several sheets of the unsintered
ceramic prior to fabricating the package. The metal paste is formed by mixing
the metal particles with organic binders and then patterning the metal lines
by forcing the paste through a screen covered by an emulsion into which the
appropriate pattern had been photolithographically etched. These layers of
interconnect traces, or conduction paths, can be connected from one layer to
the next using through-holes known as "vias." These vies consist of holes
punched in the green tape into which the metal ink is forced in the screen-
printing operation, thereby providing a conduction path from a point in one
layer a to similar point in the layer above or below it. After all the layers
are printed, they are then stacked together, with the appropriate
registration, and laminated under slight heat and pressure into a solid
unsintered block of ceramic and metal. This laminated piece can then be
heated to remove the organics and finally to sinter it into a dense, hard
ceramic. Furthermore, by appropriately shaping some of the layers, a cavity
can be formed in the package into which ultimately the active device, such as
a silicon chip, can be placed.
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Screen Printing
Screen printing mentioned above, provides an alternative mechanism for
producing a three-dimensional interconnect technology on a ceramic base. This
technology was developed in the late 1950s, at about the same time as the
multilayer ceramic tape technology, and provides some of the same functions.
In a typical application, a ceramic substrate is used onto which various
layers are screen-printed. The first of these layers might be an insulating
layer that is screen-printed, generally over a broad area. After printing,
the layer is typically dried and fired at some temperature lower than that at
which the original substrate was fired. If an insulating layer thicker than
that typically obtained by a single screen-printing layer is necessary, a
subsequent layer may also be screen-printed on, dried, and fired again. A
metallization layer may then be screen-printed through a screen with an
appropriate pattern. This, too, is dried and fired. The next insulating
layer can then be applied, typically allowing openings for vies between the
metall~zation in the first layer and the second layer. These various print,
dry, and fire operations can continue to make a multilayer interconnect board.
In contrast to the multilayer green tape technology, this method does not
easily allow for a cavity into which an active device can be sealed and
protected in an hermetic environment.
OTHER CERAMIC MATERIALS
This section describes some other ceramic packaging materials and makes
projections about those materials that could play a prominent role in the
future.
Glass and Porcelain
The earliest use of electronic ceramics was as insulators for carrying
telegraph lines, telephone lines, and power distribution lines. Ceramics and
glasses also were used in the fabrication of electron tubes, both as a tube
housing in the case of glass, and, in some tubes, as the base material with
glass-to-metal feed-throughs for the electrical conductors. The earliest
attempts at making ceramic substrates and ceramic packages employed the
materials available at the time, which were typically glasses and porcelains.
Porcelain is generally made of naturally-occurring materials, such as clays
and talcs. These substrates suffered from low strength, poor thermal
conductivity, and poor surface finish. Early in the use of ceramics for
substrates and packages, aluminum oxide (alumina) became the major material of
choice, and it continues so today. Typical compositions are made up of about
92 to 94 percent aluminum oxide, the balance being materials such as magnesium
oxide (magnesia) or silicon dioxide (silica).
The earliest metallization used was a molybdenum-manganese composition
that had been known to fire onto aluminum oxide with a very adherent bond.
This, too, was quickly replaced by either pure molybdenum or pure tungsten as
the metallization of choice in co- fired aluminum oxide ceramic packages.
These metallizat.ions continue to be the choice today. Both of these materials
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can be made to sinter at about the same temperature as the aluminum oxide
(about 1600°C) and provide reasonable electrical conductivity. However, both
of these metal systems oxidize easily and require that the aluminum oxide be
Wintered in a hydrogen or hydrogen-water vapor atmosphere.
These alumina-based compositions provide a strong material with fairly
high thermal conductivity. With tape processing, they can easily provide
high-reliability hermetic packages for active semiconductor devices.
Low-Fire Materials
Low-firing ceramic materials are generally those that fire at
temperatures below 1000°C, in contrast to the 1600 °C necessary for firing
aluminum oxide. Although a few single-phase ceramic materials do sinter at
temperatures below 1000°C, this not the general case. Consequently, typical
low-fire materials are made from glass-ceramic composites that fall into two
categories. The first is known as glass-ceramics or devitrifying glasses. A
glass is first formed by melting of the constituent materials, and then the
cooled glass is crushed and ground into a fine powder, known as a frit. The
frit is formed into the desired shape using any of the fabrication
technologies discussed earlier. The article is sintered into a dense, glassy
material, which is then annealed at some lower temperature where the glass
crystallizes (devitrifies) into a two-phase crystalline-glass composite.
The second technology is known as glass-bonded ceramics. In this case,
the desired crystalline phase is mixed as a powder with a frit of the desired
glass phase. These again are fabricated into shapes by the various forming
techniques already described and subsequently heated to sinter them into a
dense material where the glass acts as a low-temperature sintering aid that
bonds the ceramic particles together. The glass-bonded ceramic methodology is
by far the most widely used. Aluminum oxide is again the typical crystalline
material of choice. Its earliest use was in the screen-printed multilayer
process described earlier. Here, the mixture of aluminum oxide and fritted
glass is screen-printed onto a substrate and fired at temperatures typically
between 800 and 1000 °C to make a dense ceramic layer.
As the complexity of thick-film interconnect substrates increased, the
number of print-dry-fire operations exceeded 40. To simplify the process and
yet use the firing equipment already in place, some producers have recently
switched to a low-firing ceramic tape technology. Naturally, the tape
generated to fill this void is again a glass-bonded ceramic composite. Here,
the aluminum oxide powder and fritted-glass mixture is tape cast as described
earlier. These tape-cast layers can also be screen-printed with the various
interlayer metallization patterns and vies for three-dimensional interconnect
applications.
This low-fire tape process offers at least two advantages. First, it
permits use of the low- cost firing equipment available for thick- film printed
circuitry. Second, it allows the use of metal conductors other than tungsten
or molybdenum. Typical metals are silver, silver-palladium, or gold alloys,
all of which have lower resistivity than molybdenum or tungsten and thus
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contribute to faster circuit-speed designs. A current challenge in this
technology is the possible use of copper metal as a low-cost, low-resistivity
interconnect material. Implementation of this ideal is hampered by the
difficulty of preventing oxidation of the copper in typical firing
atmospheres. The usual glass phases, in the glass-bonded ceramic
compositions, are lead silicate-based glasses. If these compositions are
fired in the reducing or neutral atmosphere conditions necessary for
maintaining copper in the metallic state, the lead will partially or fully
reduce, leaving a lossy (low-resistivity) dielectric mater' al. Thus, the full
implementation of copper metallizations awaits a technology that can
successfully implement glass-bonding agents that are not easily reduced in
such atmospheres. Laboratory successes have been reported, and prototype
materials are now available.
Low-Dielectric-Constant Materials
Aluminum oxide-based ceramics and most glass-bonded ceramic materials
have dielectric constants in the range of seven to nine. The need for high-
speed circuitry demands materials with still lower dielectric constants.
Organic materials are available with dielectric constants as low as 2, but
these materials are incompatible with the high-reliability hermetic ceramic
packages. For inorganic materials, the lowest known dielectric constant is
that of silica glass at 3.9. However, the thermal expansion characteristics
and sintering characteristics of this material are incompatible with typical
processing conditions. Consequently, glass-bonded ceramic compositions are
being developed that strive to provide lower dielectric constants than those
available in aluminum oxide-based materials. The typical crystalline phase in
these materials is cordierite, a magnesium-alumino-silicate material. Also
necessary are glass-bonding agents of relatively low dielectric constants,
which typically avoid the use of lead oxide. Such materials, with dielectric
constants in the range of 5 to 6, are now available in prototype form.
Inorganic materials with even lower dielectric constants probably await
the implementation of a controlled-void technology. In this technology, the
requirement is to process materials so that a large fraction of pores can be
included, thus lowering the dielectric constant of the matrix phase.
Incorporating hollow glass spheres or possibly applying sol gel glass
technology are means of introducing controlled porosity. Closed pores are
necessary to avoid any loss of hermeticity or possible inclusion of impurities
that might lead to poor dielectric properties If this technology could be
successfully employed using silica glass ? dielectric constants below 2 might
be feasible. However, this technology will always be fraught with poor
mechanical properties, since the pores are flaws that concentrate stresses and
reduce the effective strength.
High-Thermal-Conductivitv Materials
The design of integrated circuits and hybrid integrated circuits demands
that the heat generated be dis s mated through the package. Organic packaging
materials or plastic packages typically have quite poor thermal dissipation
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POLYIMIDES IN HIGH- DENS ITY PACKAGING
Polyimides have a number of characteristics that make them important for
high-density electronic packaging. Some of these features are discussed in
the following, and some insight on their more extensive use in electronics is
provided ~
Trends in High - Dens ity Packaging
Until recently, computer systems with high- density packaging have used
one of three approaches to chip interconnection: (a) conventional epoxy
boards and multichip ceramic modules single chip carriers, (b) conventional
epoxy boards and multich~p ceramic modules with single chip carriers, or (c)
conventional epoxy boards with chips directly attached to multichip ceramic
modules. None of these systems had the capability of wiring all chips
together with a s ingle packaging level. The increasing size of central
processing units (i. e., the number of devices ire a CPU) and the importance of
eliminating interconnection delays have led to exploration of approaches that
have the potential for eliminating significant fractions of interchip signal
delays.
The published literature contains numerous descriptions of efforts to
reduce the gap between wiring density (and concomitant signal delay) on the
chip and in the package. Two of these are (a) the silicon chip carrier, in
which the interconnection between logic chips is accomplished by multilevel
thin-film polyimide insulated copper or aluminum wiring on a silicon wafer,
and (b) the hybrid ceramic module with levels of polyimide board, which is
analogous to the traditional epoxy board, but has a lower thermal expansion
coefficient and higher thermal stability for attachment of chips with a TAB-
like carrier. However, only recently have these approaches to high-density
packaging appeared in announced computer products.
The distinction between CMOS, bipolar, BiCHOS, and GaAs logic
technologies does influence the optimum approach to high-density, high-
performance packaging. CMOS and BiCMOS chips tend to have a greater number of
logic devices per chip compared to bipolar and GaAs. This leads both to
greater interconnection complexity for bipolar and GaAs logic and to an
increased emphasis on the performance of the interconnection (packaging)
technologies for these chip families. Despite this distinction, the technical
literature abounds with reports of thin-film polymer-copper or aluminum
interconnection for all the chip technologies. Consequently, it is possible
to conclude that efficient chip interconnection has become important to all
chip logic technologies.
Polvimide Processing
The processes used to fabricate polyimide-based packaging technologies
vary widely. In the extreme of "chip-like" processing, conventional chip
processes of photolithography, RIE processing, and spin coating are employed.
In another extreme, conventional board processes are employed where the
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prepreg is fabricated, electroplating is used to form metal lines, and
lamination, drilling, and electroplating are used to interconnect the levels.
Combinations of these basic approaches make use of mixes of both extremes.
One example is the use of "chip-like" processing but using "metallization"
with electroplating of copper. No distinct trends in use of these processes
are observable today, probably because the use of polyimides in high-density
packaging has yet to reach maturity.
PolYimides and Properties for High-DensitY Interconnection
The polyimides currently used in the foregoing technologies are
numerous, but all have a common characteristic. They are used when epoxies
lack adequate properties for the application. This generally occurs when
improved thermal properties (e.g., high direct solder-attach temperature) are
required, improved mechanical properties are needed (polyimides generally are
much less brittle and have greater tensile strength), or a lower dielectric
constant is required. The thermal properties of polyimides are an improvement
over epoxies in two ways: First, the thermal stability is considerably
greater, and second, the glass transition temperature, or the temperature at
which the polymer softens, is most often greater than 280 ° C . The dielectric
constant of polyimides is usually between 3.4 and 2.9, as compared to epoxies,
which are greater than 4.0.
Today, many polyimides are available for high-density packaging
applications. The properties of these materials range widely in a number of
categories: glass transition temperatures between 250 and 400°C are
available; mechanical properties ranging from brittle to very tough may be
achieved; thermal stability at 250 deco 400°C is possible; dielectric constants
from 2.65 to 3.4 are typical; adhesion to the ceramic, polyimide, SiO2 , or
metal interfaces varies widely, but generally requires an adhesion-promotion
agent; the stress in a polyimide film varies widely among commercially-
available materials (amorphous polyimides generally have a film stress of
about ~ to 7 Ksi, whereas ordered polyimides may have film stress as low as 1
Ksi); and planarization also varies widely between polyimides but is generally
dependent on the percent of solids in the formulation.
The thermally-induced stress in polyimide packaging structures is
usually dominated by the high ICE of these materials. Recently, a
breakthrough has occurred with the availability of low-TCE polyimides. These
materials may have linear expansion coefficients of 6 X 10-6/° C compared to 35
x 10-6/°C for conventional polyimides. In addition, these materials may be
tailored for TCE matching. This new family of materials will likely be used
widely in high-performance thin-film interconnections. While these materials
offer a significant advance in the reduction of stress in interconnection
structures, further improvements in self-adhesion of these materials are
desirable.
Although the packaging process engineer has this wide variety of
properties to choose from, it is generally true that the best properties in
each category are not available in a single material. Consequently, selection
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of a polyimide for a packaging application may be a complex process in which
compromises must be made.
Photosensitive Polyimides
The processing of polyimide films for high-density packaging is often
complicated by the necessary patterning of the films. This patterning is
generally accomplished for board-like structures by drilling, by oxygen
reactive ion etching (RIE) for fine-line features, or by etching with a strong
base or hydrazine. Each of the last two methods requires separate masking
steps that add to the complexity of processing. Considerable simplification
of serial-process fabrication of polyimide-based packaging technologies can be
realized with photosensitive polyimides. These materials have been
commercially available for some years from a number of chemical companies in
the United States, Europe, and Japan. Japanese chemical companies, in
particular, have been most aggressive in making photosensitive polyimides
commercially available. Again, as in the case of conventional polyimides,
choosing a photosensitive polyimide for a packaging application is a complex
process in which the optimum combination of properties is not available and
compromises must be made. One example is the fact that most photosensitive
polyimides shrink about SO percent in processing from the lithographic imaging
to final cure. This shrinkage leads to limitations in feature size
resolution, which currently is in the range of 25 Am for thicknesses greater
than the 8 Am thickness used in packaging technologies.
General Availability of Technical Information on Polyimides
Packaging engineers who seek to use polyimide materials are often
confronted with the need for detailed information on their chemical, physical,
and process characteristics. Chemical companies have traditionally supplied
customers only sketchy information on these materials. University research on
the chemistry physics, and process characteristics has not been a popular
endeavor, as this has been considered an "old" field of research. Large
companies that intend to use polyimides in new technologies have conducted
their own R&D but have not published this information widely. Consequently,
detailed scientific understanding of polyimides, which forms the basis for a
well - engineered packaging ~cechnology, has not been available to the whole
industry. The technical vitality of the U.S. high-density packaging industry
would be well served if both chemical companies and universities placed
greater emphasis on providing this information.
Benzocyclobutane (BCB) is a polymer recently introduced that has great
promise as an interlayer diel ectric and other applications. The dielectric
constant i s about 2.7 and the loss is very low, as expected for hydrocarbons .
Polymerization does not release volatiles and high glass transition
temperatures, greater than 350°C, are achieved. This material exhibits very
low moisture absorption and is chemically extremely stable. Although there is
much less industrial experience with BCBs, some commercial applications are
already appearing and BCBs could become the polymer dielectric of choice in a
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wide range of circuits. A photoimageable BOB has not appeared yet, but it can
be plasma etched through a lithographic mask.
Polymers in Future High-Densitv Interconnection Technologies
The trend toward thin-film interconnections in high-density packaging
appears to be set and will continue for the foreseeable future. With the
evolution to higher-performance requirements, incremental improvements in the
properties of polyimides or polymers used as insulators will be sought by the
industry. Required improvements will be needed by the industry, and will
probably occur in two categories: (a) photosensitive polyimides with greater
lithographic image resolution and (b) polymer insulators with lower dielectric
constants. It would be useful if easily processible materials with dielectric
constants as low as 2 were available. These requirements present a
significant challenge to the chemical industry because they are not currently
available .
TAPE AUTOMATED BONDING
Tape automated bonding (TAB) uses a premanufactured lead frame as a
substitute for wire bonding. The lead frame presents a uniform array of inner
leads to be attached to the bond pads on the surface of the die. The die and
leads are then excised from the lead frame, and the outer leads are bonded to
a package or a multichip substrate. The TAB lead frames are manufactured in a
continuous process and are available in reel, strip, or slide format. All the
leads can be bonded to the die simultaneously. TAB is often preferred over
wire bonding for multichip modules because it can accommodate more leads per
chip (more than 300) and higher clock frequencies.
There is a cost overhead for the tape design and tooling for each chip
size, and, therefore, TAB is best suited to high-volume applications. TAB is
routinely used to fabricate liquid crystal television displays, which require
many leads for relatively small die sizes. One brand of hand-held televisions
contains TAB with 80 Em lead pitch (about 300 leads per linear inch). The
first U.S. applications for high-lead-count TAB will be in computer work
stations. This application requires packaging of high-lead-count devices (up
to SOO per chip), with operation clock rates of 50 to 100 MHz, and the ability
to be manufactured in volumes of tens of thousands. Once these requirements
are met, TAB use will then spread to many other applications . Wire bonding
will continue to be used for single-chip packages with up to 200 leads and
also for prototyping of multichip modules.
From a materials point of view, TAB consists of copper conducting
fingers carried on a polyimide film. The joint between the TAB tape and the
chip bonding pad requires a metal "bump," either placed on the chip or on the
tape. Because TAB tapes are very thin, the mechanical modulus of the
polyimide is an important factor in simultaneously positioning all of the lead
fingers in register with the bonding pads. Thermal expansion is also
important.
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The expendability of TAB technology from the present 200 I/Os per chip
to the expected 600 I/O chips of the mid- 1990s will require much finer-pitch
inner-lead peripheral connections or area array chip - to - TAB connections . Both
approaches are difficult, if not impossible, with present TAB substrate
materials. TAB carriers with lower TCE and higher modulus are required. The
first of these improved substrates is available in the form of a lower-TCE
polyimide, but further substrate materials improvements will be required to
reach the mid-1990s requirements.
TAB has been a promising technology for many years, but it is still not
widely used in the semiconductor electronics industry. At this time, nearly
every major semiconductor manufacturer is either using or evaluating the
technology. The committee was not in complete agreement regarding the degree
of market penetration and the time scale for penetration.
DIAMOND
Diamond is among the most interesting of all materials (DeVries, 1987).
In the familiar single-crystal form, it is far too expensive to be employed in
ordinary packaging * The phys ical properties are remarkably attractive,
however, and efforts to grow diamond, or di~mond-like, films have persisted
through the years. Within the past decade, films have been successfully
produced by chemical-vapor-deposition (CVD), and research activity in this
technology has accelerated. Ion beam epitaxy has also been employed to
produce films with good properties that can be deposited on various
substrates. Although growth rates are small and conditions involve moderately
high temperatures for the substrate, good progress is being made, and it is
reasonable to expect that diamond-film passivation layers will become possible
within a few years.
Among good dielectrics, diamond has uniquely high thermal conductivity,
and CVD films have approached values typical of bulk crystalline diamond. The
value of 20 W/cm°K at room temperature is an order of magnitude better than
BeO and four orders of magnitude better than epoxy. Hardness, relatively low
dielectric constant, and good optical properties also favor diamond films. At
liquid nitrogen temperature, thermal conductivity is above 100 W/cm°K.
Applications that would benefit from the singular properties of diamond
films include chip passivation, substrate coatings, and interlayer dielectric
layers. The design possibilities are sufficiently removed from present
materials so that new strategies of thermal management could arise based on
the s e new diamond f i lms .
SUPERCONDUCTORS
It has been recognized for many years that superconducting materials
offer great promise for high-speed electronics (Hunt, 1989~. A number of
organizations have worked on the development of Josephson junction technology,
and at least one company, Hypres, has successfully marketed commercial
devices. There are important differences between silicon electronics and
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Josephson junction electronics (e.g., voltage level), and it has been
difficult to overcome the momentum of the more established technology. Not
the least of the Josephson burden is the requirement for liquid helium
cooling. With the discovery of high-temperature superconductors (HTSCs), the
comparisons have been reopened, because liquid nitrogen cooling is easier and
more economical than cooling with heli~,rn.
The problem of packaging and interconnection of Josephson circuits is
beyond the scope of this report. There is, however, the possibility of
employing superconducting striplines as interconnects in printed circuit and
multichip module structures. As lateral dimensions of circuit lines shrink
(see Figure 2-8), the line resistance can become a problem; for example, a 2
Am x 8 Am copper line has a resistance of 10 ohms per cm at room temperature
but only about 2 ohms per cm at liquid nitrogen temperature. As the line
resistance becomes an appreciable fraction of the line impedance (50 to 70
ohms), the speed of signal transmission decreases, a feature that favors low-
temperature operations.
The new HTSCs are ceramic materials that will require considerable
development before their promise can be realized in practical circuits. These
materials must be processed at high temperatures and must be protected from
atmospheric moisture. In addition, electrical contacts with them to other
metals are not easily made, and the properties at high frequencies are less
than ideal. These are early days in the HTSC field, but, with a massive level
of research under way world-wide, the problems will be overcome.
Interconnects for advanced electronics are under consideration as an early
application. Unlike superconductor wire applications, much of the ductility
and flexibility requirements in interconnections are less demanding.
There can be little doubt that HTSCs will become a part of interconnect
structures, although applications are probably several years away. Research
on all aspects, scientific and technological, should be strongly encouraged,
bearing in mind that materials interactions and process compatibility will be
particularly important.
COMPOSITES
Composite materials represent the extent to which materials are being
engineered to achieve design intent; for example, strong fibers in polymer
matrices have had an enormous impact on the construction of aircraft and other
aerospace structures. In electronics, composites have long been used as
printed wiring substrates (e.g., FR-4) and silica-filled encapsulation
epoxies. Today, new composites are beginning to appear that will broaden the
range of materials combinations found in electronic structures.
The more traditional fiberglass substrates (woven E-glass mats embedded
in a bisphenol-A epoxy matrix) are being replaced by materials that give
better dimensional control, lower dielectric constant, and greater operating
temperature range. Polyimide fibers can be designed with small and even
negative coefficients of linear expansion, and these are beginning to find
their way into electronic substrate composites. Expanded teflon fibers may be
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introduced into epoxy matrices to achieve lower dielectric constant. More
highly functionalized epoxy matrices offer better dimensional control and
higher glass-transition temperatures. Polyimide matrices also offer high-
temperature performance. This latter area is one of intense activity, and new
systems can be expected to increasingly penetrate the high-density PUB market.
Research in this area will benefit from closer coupling with systems
designers.
Filled-plastic encapsulants today employ silica almost exclusively, but
the opportunity exists to enhance thermal conductivity by introducing
alternative fillers. The thermal conductivity of the encapsulation compounds
can be improved by factors of two to six by introducing compounds such as
alumina, magnesia, and boron nitride at the expense of larger (less than 50
percent) coefficients of thermal expansion (CTE). Research in this area could
yield important results (see the first section of this chapter).
Ceramic-matrix and metal-matrix composites also are available, and the
field is developing. Opportunities for matching CTEs of composites and
semiconductors while improving thermal conductivity are illustrated in Figure
5-2 cited earlier. Their use in printed wiring and multichip modules is
suggested, and some applications already exist; these materials also have been
used for housings for microwave and power units. This is an area in which
significant work is being done, both in the United States and overseas, but
the work is not very visible. Improved composite materials for packaging and
interconnection should be a significant focus of future work because the
opportunity to design materials with desired substrate properties is worthy of
further attention in the context of high-density electronics.
The high thermal conductivity of carbon fibers suggests their use in
composite materials for heat sinks. Carbon-fiber-reinforced copper, for
example, can be designed for good thermal conductivity coupled with weight
reduction. Also, carbon-fiber-reinforced epoxies can be made with high
thermal conductivity, dimensional control, and ease of fabrication. In these ,
continuous fibers are preferred. Here again, composites offer the flexibility
to engineer materials with desired properties.
Multichip modules, as discussed in Chapter 3, offer high-density
interconnections on a planar surface. These modules may have hundreds of
I/Os, usually arranged around the periphery of the module. They may be
attached to a mother board through pin grid or pad grid array terminals, or
they may be combined in a stacking fashion to form supe`modules with short
interconnect paths. The z-dimensional connections can be made by special
composite materials that electrically conduct in the z-direction, yet are
highly resistive in the x- and y-directions. The conductors are metallic and
are oriented In a matrix that may be ceramic or polymeric. Photodefined holes
are etched in the ceramic substrate, then filled with wadded-up wire ("fuzz-
button"~. This arrangement can interconnect facing surface pads reliably
without solder; i.e., pressure alone suffices (see Appendix D).
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Polymer systems can be made to conduct by using magnetic alignment of
nickel balls, oriented wires, or balls of metal whose diameter is greater
than the layer thickness. These composites may be held in place mechanically
or by adhesives. Many contacts can be made in a single operation, thus
facilitating assembly. These composite anisotropic conductors are still in an
introductory phase and have not been demonstrated in high-reliabili~cy, high-
density electronic systems. They have been employed in small television
displays, where a large number of contacts (1800) is required and disassembly
is important. These techniques offer ease of assembly and other advantages,
but much testing remains to demonstrate the reliability needed in high-
density electronic systems.
MATERIALS FOR VERY-HIGH-FREQUENCY DIGITAL SYSTEMS
Very-high-frequency digital electronic sys tems are extremely demanding
in terms of materials properties. Generally, inorganics are used as
substrates for the first level of interconnects, whereas organics serve as
interlayer dielectrics. High-frequency structures require low-dielectric-
constant values, whereas the power plane will need very high (' to store
charge very close to the chips it is powering.
Inorganic dielectrics generally have high dielectric constants, i.e.,
('2 3.8. Thus, they are not likely materials of choice for interlayer
dielectrics. Ceramic layers can be prepared in porous forms that can achieve
(' < 2, but it remains to be demonstrated that these materials have sufficient
mechanical durability and can be prepared with a smooth surface. Process
compatibility for building multilayer structures must be established and long-
term stability characterized. Even so, this is an interesting class of
material that offers radiation resistance and low high-frequency loss.
Ferroelectric ceramics can offer high - dielectric - cons tent ~ ~ ' >103
capability for essential charge storage near active devices. For high-
frequency applications, it will be necessary to demonstrate that the material
can respond rapidly enough to deliver the charge in the time scale required.
In additions the dielectric constant of ferroelectrics often decreases
dramatically as frequency is increased through the GHz range.
Polyimides have been favored as ~nterlayer dielectrics for MCMs, and a
great deal of development work has been focused on such multilayer structures.
As circuit speed is pushed higher, lower-dielectric-constant materials will be
required, and polyimides will be displaced. Polyimides absorb water, which
leads to E' variability and high-frequency losses (I"). Hydrocarbon and
fluorocarbon polymers are most promising for ['<3 and low dielectric loss
(~tt<10-3). Considerable development effort will be required to provide low-
dielectric-constant layers that are process-compatible, exhibit good adhesion,
and satisfy all the other design requirements.
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MATERIALS FOR CONNECTOR APPLI CATIONS
Connectors are necessary in high-density electronic systems to
facilitate assembly, repair, and maintenance. Unfortunately, connector design
historically has been handled as an afterthought to system design. Although
this approach has created serious reliability problems in the past, it has not
necessitated a redesign of entire systems. As system performance increases,
as measured by signal rise time, electrical discontinuities that are
transparent at large rise times cause serious signal reflections. Physical
design of connectors that provide thousands of connections and are capable of
handling signals with less than 100 psec rise times are a significant
technical challenge.
From a materials standpoint, advanced connectors will be driven to the
most reliable metallurgy, e.g., gold mated to gold on palladium. The choice
of insulator is made on the basis of mechanical strength. Because of the very
small cross sections of the molded parts, thermoses materials are favored--
e.g., polyethyleneterephthalate, polybutyleneterephthalate, and polyphenylene
sulfide. For higher-temperature applications, polyethersulfone and
polyetherimide can be employed. Physical design of high-density connectors is
becoming a major challenge, with materials properties and processing occupying
an important position in meeting the performance needs.
THE THERMAL CONDUCTION MODULE
IBM's thermal conduction module (TCM) has been at the leading edge of
integrated circuit chip packaging for some time. This very significant
accomplishment has taken a long time to develop since its beginning in 1964.
This concept, and early work, started in a program with the appropriate name,
"next-generation technology" (NGT). A technical description of the TOM was
published by Blodgett (19831. The following discussion briefly describes the
his tory of how the TOM evolved .
The NOT program was started in January 1964, and in April 1964, IBM
announced the System 360 with its solid logic technology ~ SLT) . The SLT
program made use of small silicon chips containing single transistors that
were attached to 1/2- by 1/2-in. ceramic substrates containing 16 pins that
were soldered into printed-circuit daughter cards. Small copper spheres, plus
solder, were used to connect the inverted transistor chips to the thick-film
pattern on the ceramic substrate. Resistors were fabricated on the chip by a
silk-screen process, as was the wiring on the chip. The resistors were later
trimmed to value by a "sand-blasting" operation.
Within IBM, in 1964, there was a small, but articulate, faction that
argued that SLT was threatened by integrated circuits. This issue of SLT
versus integrated circuits quickly became polarized and highly emotional. The
NOT program, from its inception had, decided that integrated circuits and
monolithic memories were the correct technical thrust for the future, and an
effort was made to stay out of the highly emotional issue, but with little
success. How to package integrated circuits was not resolved within the NOT
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program until about August of 1964. At that time, the NGT program defined a
four-phase approach to solve the packaging problem of integrated circuits.
For phase 1, it was proposed to put integrated circuit chips on the SLT
substrate, which would provide the benefits of integrated circuits without
having to develop a whole new package. In addition, the SLT module was
consistent with the level of integration on chips at that time. Phase 1 later
became known as the monolythic systems technology (MST), which was the
technology used in IBM's System 370.
NOT's phase 2 proposed using a 1 by 1 in. ceramic substrate, which, with
its larger area and more I/O pins, could support chips with higher levels of
integration. Phases 1 and 2 were based on established packaging technologies,
while still concentrating on learning how to produce integrated circuit chips
to go on those packages. Phases 3 and 4, being further away in time, proposed
a significant departure from the SLT module.
The NGT program recognized that the level of integration would
constantly increase with time, and thus a viable packaging strategy must take
this into account. It also was recognized that the exponent in Rent's rule
was less than 1. This meant that the ratio of I/O pins to circuits would
decrease with increasing levels of integration on the chip, a reasoning that
held for the next level of packaging as well. Contacts between levels of
packaging take up space, are costly, limit performance for high-performance
systems, and can create reliability problems. By going to higher levels of
integration at all levels of packaging, one or more levels might be
eliminated.
During the period from 1964 to 1966, the NGT program had a joint effort
with Texas Instruments (TI) that was structured to explore the future problems
of large-scale integration (LSI). In this joint program, TI supplied IBM with
wafer-scale integration consisting of 9 wafers with 120 circuits per wafer
mounted in 9 modules. A small system, using these modules, was working by
early 1966. TI used pattern interconnection in fabricating the wafers. At
that time, fixed pattern interconnection could not provide LSI capability.
The NGT program selected multilayer ceramics (MLC) as the technology
with which to construct the modules for phases 3 and 4. Phase 3 was targeted
at future cost-performance types of systems, whereas phase 4 was focused on
future high-performance systems. The plan in phase 4 was to use high-
performance emitter coupled logic (ECL) on integrated circuit chips. High-
performance circuits consume high power per circuit. However, since one NGT
objective was to place as many circuits on the chip as the manufacturing
process would allow at a given time, a way had to be found to dissipate all
the power produced by the many chips on a module. It was felt that
fluorocarbons could be used in the module to carry heat from the chip to a
heat exchanger on the module.
Use of an MOM with signal conductors embedded in ceramic that had a
dielectric constant of approximately 9 caused a debate within IBM. The debate
ensued over the advantages of transmitting a signal from one chip to another
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through a relatively low-dielectric-constant material, such as FR-4 epoxy,
versus a high-dielectric-constant material, such as alumina ceramic. The
velocity of propagation is higher in FR-4 than in ceramic, but the distance
can be much shorter in ceramic. Only relatively recently has a consensus
emerged that supports the NGT researchers.
By early 1966, IBM decided that a replacement was needed for System 360.
To do this, a monolithic systems technology a (MST) program was initiated
based on the NGT phase 1 proposal and staffed by NGT people who had been
previously asked to concentrate on the highly aggressive phase 4 program. At
this time, the NGT program had rudimentary multichip, multilayer ceramic
module hardware working. Domestic work was stopped at IBM. Fortunately, the
NGT program had generated interest in multilayer ceramics in IBM's Boeblingen
laboratory, and researchers there continued and improved on the multilayer
ceramics work that had been started in IBM's domestic laboratories. The
Boeblingen effort became the basis for IBM's present TOM when this technology
was reintroduced to the United States in the mid-1970s.
The purpose of recounting the early history of multilayer ceramics at
IBM is to emphasize the point that developing new structures employing new
materials is a long and difficult process. When such a process is successful,
the payoff can be quite dramatic, as has been demonstrated at IBM.
REFERENCES
DeVries, R. C. 1987. Synthesis of Diamond Under Metastable Conditions.
Annual Reviews of Materials Science, vol. 17, pp. 161-187.
Hunt, V. Daniel. 1988. Superconductivity Sourcebook. New York: John Wiley
~ Sons' pp. 38-39.
Blodgett, A. J. 1983. Microelectronic packaging. Scientific American, vol.
249, pp. 86-96, July.
Representative terms from entire chapter:
dielectric constant
