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Chapter 1
INTRODUCTION
In the 40 years since the invention of the transistor, much attention
has been given to silicon devices and integrated circuits (ICs). (See
Appendix A for some terms and acronyms.) The impact of silicon electronics
triggered the era of information processing and continues to produce amazing
progress. The size of the circuit elements, the speed of their operation, the
minimal power consumed, the cost per element, and the reliability of the
circuits have improved dramatically. Today, silicon integrated circuits
(chips), about the size of a fingernail, may contain a million transistors and
cost a few dollars or tens of dollars (or hundreds in extreme cases ) ,
depending on the type and production level. There are good reasons to expect
that some chips will contain a billion elements by the end of this century,
and other characteristics will be improved as well. The recognition and
praise lavished on silicon electronics over the past 4 decades is entirely
justified, and the future remains promising.
And yet, integrated circuit chips ore not useful until they have been
woven into the fabric of interconnections and packaged. Packaging and
interconnection (interconnects) provide structural support, mechanical and
chemical protection, thermal management, power, ground, and signal
transmission, including timing. The package must be durable and
manufacturable and allow access for testing and repair. System performance in
today's advanced systems is as likely to be limited by packaging and
interconnection as by the chips themselves. In this report, high-density
electronic packaging and interconnection will be described from the point of
view of the materials of construction. The time frame of this report covers
the present (1989) and the period in which present practice evolved and
extends toward the end of the century. It is probable that reasonable
predictions can be made extending for ~ or lO years, but foreseeing system
trends in the next century is highly speculative.
The many different sectors that encompass the field make it difficult to
separate those to include or exclude. Consumer products, computer mainframes,
supercomputers, telecommunications switching, personal computers, work
stations, automotive components, and various military classes and other
subareas all represent modern practice in the context of specific needs. Some
conswner products use an aggressive packaging strategy. Very-high- frequency
systems are often not high density. Advanced areas (e. g., computer
mainframes ~ are inherently expensive and thus do not represent the leading
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Representative terms from entire chapter:
bonding pads
10
edge of developments in other applications. Therefore, this report concerns
itself with high-density packaging, in the sense of chips with large numbers
of I/Os (inputs, outputs, or both) and the need for high-speed communication
between chips.
Materials properties play a critical role in system performance and in
manufacturing process effectiveness. The materials in use have evolved along
with the physical design of the electronic systems, and today's structures
represent engineering optimization of many factors. It is of little benefit
to consider the properties of the materials outside the context of the
application. Furthermore, the packaging and interconnection structures are
composites containing many different materials in close proximity. Thus,
interracial properties and materials compatibility factors are often more
important than bulk properties of the isolated materials. The dependence of
the materials properties on the manufacturing process is also important.
Electronic packaging includes all structures that are designed to
protect the integrated circuits, the attendant interconnections and the
related circuitry from physical damage and any other impediment to achieving
design performance. Interconnections include all means of communication
(power, timing, data, results) from one integrated circuit to another or from
one system of circuits to another. Interconnections on the chips themselves
is not considered in this report, and interconnection by means other than
electrical (e.g., photonic) are also excluded. Thus, the subject matter of
this report concerns materials issues involved in electric circuits that run
from the bonding pad of a chip through the chip package (if any) by means of
lead frame (or other fan-out to leads), through strip-line circuits on a
substrate that may be connected by "vies" perpendicular to the plane of the
substrate, and end at other integrated circuit bonding pads; it also includes
other components or connectors that lead to other circuit boards, shelves, or
frames. The physical nature of this packaging and interconnection hierarchy
is indicated in Figures 1-1 through 1-7.
11
?~ -it /, ///~/li//~/l
FIGURE 1-2 Schematic representation of a chip carrier. The chip is die
bonded to the package. The signal, power, ground, and timing leads are wire-
bonded to bonding pads on the chip. (A TAB inner lead frame could replace the
wire bonds shown.) The exterior case may be premolded plastic (as shown) or
ceramic.
~ ~,~
\
, ~
A, ~
~ r\,, 7t
FIGURE 1-3 Molded plastic quad design or plastic leaded chip carrier (PLCC).
The chip is die-bonded to the paddle, which is connected to one or more ground
leads. Signal, power, ground, and timing leads are connected by wire bonding
pads. (A TAB inner lead frame can be used for this purpose. ~
An,/
~,~,~/
FIGURE 1-4 Cutaway of a PGA. The chip is die-bonded in the ceramic cavity
and wire-bonded to the conductor fan-out, which is plated onto the ceramic.
The outer end of each fanout finger is terminated onto a brazed pin, which is
inserted into a through-hole on the PWB. This package can then be sealed
hermetically with a lid (ceramic or metal). Similar packages with surface-
mount leads are also employed. The device is shown inverted, and in use the
active side of the chip would face the PWB (face down). The pins can be made
to exit the ceramic on the opposite side (face up). The face-down option
shown offers a favorable surface for heat-sink attachment.
. ~
-
FIGURE 1-5 A field of solder bumps with device ready for mounting in C4
attachment (controlled collapse chip connection).
13
/
/// ~ -A A:
\
FIGURE 1-6 Direct chip attachment with protective polymer overcoat (''glob
tops.
/
:_ ~ Hilt
- ~
~ :~': ~/
,~
./
FIGURE 1-7 Printed wiring board circuit shown in cutaway to reveal inner
connector layers and vies. A surface-mount device (left) and a through-hole
device (right) are illustrated. Note that surface-mount devices can be
mounted on both sides of the board (as shown) and do not consume valuable
inner layer space with the through-hole .
14
Integrated circuit chips are encapsulated in three types of packages:
dual in-line packages (DIPs), chip carriers (CCs), and pin grid arrays (PGAs).
Each option has many variants, and only the most elementary description is
attempted herein. In terms of numbers of units manufactured, the DIP is most
important. Chip carriers, however, are now being adopted widely and should
rival DIPs in numbers within a few years. In monetary terms, DIP and CC
packaging are comparable today, owing to the higher average cost per unit of
the CC option. PGAs are very expensive and are employed only for chips with
large numbers of external connections (I/Os).
The magnitude of the packaging market for 1987 is summarized in Table 1-1.
The $2.0 billion packaging total is part of a total U.S. IC market of $9.3
billion. The 1987 market for printed circuit boards amounted to $5.1 billion,
and edge connectors for boards amounted to $0.8 billion. Thus, the 1987
silicon cost of $7.3 billion was supported by more than $7.9 billion in
packaging and interconnection. These numbers are imperfect, owing to the
omission of captive production by equipment suppliers and other factors, but
nonsilicon costs are comparable to and probably greater than silicon costs.
The numbers also omit the hybrid market (U.S. 1987, about $4 billion), a
substantial portion of which can be classified as interconnection and
packaging. In view of the rate at which silicon costs are dropping, this
spread in costs will increase unless packaging technology is given more
empha s ~ s .
Table 1-1 U.S. Packaging Market, 1987 Estimate
Type Units Average Cost Total Cost
(billion) (S/unit) (billion $)
DIP 7.4 0.13 0.93
CC 0.7 0.68 0.47
PGA 0.05 6.61 0.31
Other 0.7 0.34 0.25
Total (avg.) 8.9 0.22 1.96
The lead frames of DIPs are inserted in holes (vies) that extend through
the printed circuit board. These holes are usually drilled on a 100-mil (0.1
in.) grid and each (copper plated) hole passes through each layer of a
multilayer circuit. Chip dimensions are conventionally discussed in terms of
micrometers (pm). Printed wiring interconnection structures are usually
described in terms of mils (i e., 0.001 in.~. Advanced interconnection
structures may involve both units; 1 mil is equal to 25.4 ~m. The holes
account for an appreciable fraction of the board area and thus limit the
number of interconnections that the board can support. Chip carriers (CCs
are bonded only to the top surface (surface mount assembly, SMA) of a
multilayer circuit, and no grid of holes are needed. With SMA, components can
also be mounted on both sides of the board Therefore, CCs with SMA are
15
capable of a higher density of interconnection, which is an important driving
force for CCs to displace DIPs. Pin grid arrays (PGAs) are also available in
surface-mount form.
Chips are attached to the lead frame by "die-bonding" on the back side
with solder or conducting adhesive, and the bonding pads are connected to the
lead frame fingers by means of fine gold or aluminum wires. A "ball" bond is
formed at the chip bonding pad and a "wedge" bond is foxed at the inner lead
frame finger. The process of wire bond formation is automated and very fast,
although they are done serially, one at a time. The bonding pads on the chip
are usually restricted to the perimeter. The spacing between bonding pads is,
however, limited (about 6 mils) by the size of the wire-handling tool, which
is an important design factor affecting chip die size for circuits with a
large I/O count. An alternative to wire bonding is tape automated bonding
(TAB), in which the lead frame is a thin copper layer supported by polyimide
film and all the inner fingers are bonded to the chip pads in a single
operation. By supporting the leads on film and eliminating the wire bonding
tool, finer lead spacing (about 4 mils) and higher interconnection density are
pass ible . This technology has been available for many years, but no large-
scale displacement of wire bonding has occurred. Difficulties involved in
preparing the pads or tape fingers ("bumping") and in the simultaneous bonding
operation are significant.
Preformed packages (premolded plastic or ceramic) are sealed by affixing
a lid. The chip resides in a cavity. If the package material is ceramic, the
seal may be hermetic, a feature required for most military and other high-
reliability circuits. All plastic materials are permeable to some degree, and
thus hermeticity cannot be achieved today in plastic packages. Even so,
plastic packages can be highly reliable. Plastic packages can be premolded,
but they are more likely to be transfer-molded after the wire bonds have been
formed. In this process, the chip, bonded to the lead frame, is placed in a
mold tool and molten plastic is forced in to fill the cavity completely. Good
adhesion between the plastic and the chip and the lead frame is achieved,
which makes the structure durable. After the chip has been sealed in its
package, it can be tested, transported, and mounted on a printed circuit
board.
An alternative approach involves direct mounting of unpackaged chips on
circuit boards. In the soldering process, the chips "float" (face down) on
solder balls that form the conducting bridge to the circuit. This approach is
sometimes called C4 bonding (for controlled collapse chip connection). The
bonding pads are not restricted to the periphery of the chip, thereby offering
considerable advantage. Other "bare chip" options exist, including the use of
face-down, "beam- lead'' or TAB lead frame arrangements, and also face -up wire-
bonded configurations. Following assembly, these chips may be covered with a
plastic coat ("glob top" ~ for protection (see Figure 1-61. Chip-on-board
(COB) interconnection is not amenable to the burn-in and testing required for
military use, and hence this approach has been more popular in consumer-grade
systems.
Printed circuit boards may have only one or two layers of circuitry, but
high-density interconnection usually implies many layers, typically eight but
16
possibly as many as 40. Patterns of metal are defined photolithography by
means of a resist process on interlayer substrates, whereby t'viat' (i.e.,
through-sheet) connections are formed. The various layers are then "piled up"
and processed to form the registered multilayer structure. For ceramic
structures, the metals can be screen-pi-inted in paste form, and the lamination
is accomplished by "firing" at a high temperature (about 1600°C for alumina).
Co-fired ceramics undergo large material shrinkage during processing, and thus
present registration difficulties fin multilayer structures. For epoxy-glass
boards, copper patterns are etched (or plated) on partially-cured (B-staged)
epoxy, and final bonding and curing are carried out under pressure at about
200°C. Vias are formed by electroless plating, after lamination for through-
hole boards and before lamination for surface-mount boards. These processes
are extremely demanding because the circuits are large in area and layer-to-
layer registration must be maintained.
Figure 1-8 illustrates progress in chip and printed wiring board (PWB)
miniaturization as measured by linear dimensions of conductor
width or smallest circuit feature. Although there is much detail that is
obscured by these lines, the progress is dramatic and real. Clearly, on-chip
features have been reduced at a rate that consistently exceeds that for PUB
patterns . Where chip features were an order of magni tude smaller in the 1960s
than earlier designs, they are now nearly two orders of magnitude smaller than
that. This, and other factors, will lead to an increasingly important
intermediate level of interconnection. In fact, interconnect structures of
intermediate size have existed right along in the form of thin-film hybrids.
At this time, however, there is a great proliferation and diversity in the
development of multichip modules (MCMs) that are at least a significant
advance in hybrid technology and may be considered a new level of packaging.
Multichip modules will probably become component-assembled on both hybrids and
PWBs.
Multichip modules typically consist of a ceramic base section with power
and ground planes. Interconnect circuitry is placed on top with fine metal
traces, usually copper, separated by organic dielectric interlayers, usually
polyimide. Because of the fineness of the signal traces, two layers on a MCM
can replace many (>20) signal layer`; of 8 thick-film (screen-defined)
structure.
In some MCMs, silicon wafers are employed as the substrate in place of
ceramic . This form of MCtt should not be confused with wafer- scale integration
(WSI ~ technology, in which both chips and interconnections are fabricated on a
single silicon wafer to form an independent system or subsystem. Yields are
nearer 100 percent, and desk An redundancy i s an inherent feature of WSI . This
is a very demanding technology, and success has not been achieved, despite
vigorous and wetl-conceived efforts. In the MCM approach, interconnect
structures are built up on the silicon wader, and tested chips are attached.
The use of pretested chips greatly~reduces yield loss. It seems evident that
MCMs will play a central role in t~igh~de~sity electronic packaging over the
next decade.
17
r~-l-1~-I-r-~--~-l If I ~ I i ' I I I I' ~ ~ I II
500
200
100
50
-
'~' 20
~ 10
loll 5
2
1
0.2
~ PWB's
_' 1 1 ~ I I I I 1 1 1 1 ,, , I I I 1 1 , , , ~ 1 1 1
1970 1980 1990
3/89
Figure 1-8 Progress in IC chip (in development) and PUB miniaturization (line
widths expressed in ~m). In Chapter 2 a more conservative extension of the IC
line is developed.
Solder is employed for attaching chip packages to circuit board
substrates. For DIP through-hole mounting, a solder wave is passed across the
back side of the board (i.e., on the side with no components), which subjects
the board to a brief thermal shock, although it is benign from the point of
view of the components. For a surface-mount assembly, the entire structure
must be brought to solder reflow temperature, which can place an unusual
stress on the components. As the assembly is cooled following the soldering
operation, thermal stress can arise if the thermal coefficients of expansion
(TCEs) of the chip package and board substrate are not closely matched. This
problem is accentuated as package size increases. When the TCEs are not well
matched, the chip package must be provided with compliant leads that can
adjust to the dimensional mismatches that develop with temperature changes.
Conductive polymers, both isotropic and anisotropic, are being developed to
replace solder, but widespread use in the next decade is unlikely.
18
The materials of electronic systems can be summarized in terms of
relatively few basic elements and compounds. The chips are silicon with
aluminum metallization, and with silicon dioxide (silica), silicon nitride, or
polyimide as the dielectric. A glass (P-glass) or silicon nitride is used for
passivation. The chips are packaged in epoxy molding compounds filled with
silica powder. Electrical connections are made with gold wires that go from
chip bonding pads to lead frames constructed of copper or an alloy of iron and
nickel. The packaged chips are attached by solder to printed circuit boards
composed of epoxy-glass (or sometimes polyimide) substrates that support the
copper interconnection patterns. In some cases, alumina substrates are
employed with interconnections of refractory metals. Connections to other
boards are made through connectors composed of molded plastic (e.g., diallyl
phthalate, polyphenylene sulfide, etc.) with beryllium-copper contact fingers
and cables with copper conductors insulated with extruded plastic.
This summary, while substantially accurate for the great majority of
circuits, fails to reveal the enormous amount of materials engineering work
that makes possible the manufacture and use of electronic systems. Each
material has to be carefully tailored for specific purposes, and issues of
material compatibility are of critical importance. The process sequence,
often involving hundreds of steps, must be such that conditions later in the
manufacturing sequence do not undermine structures formed earlier. This
abbreviated description includes only the materials that remain in the final
product. In fact, many other materials are necessary to the processes that
give rise to the structures but are not an integral part of the final
structure. Process control is increasingly critical. Thus, packaging
materials present challenging demands. The package must provide timing
information to all parts of all chips with manageable skew. Data must be
delivered to and from chips with delays that are consistent with chip circuit
switching times, and an increasing number of access points are required as
chips evolve. Electrical power and ground must be supplied over leads having
small impedance, which translates to extremely short paths. The heat
generated by the chip circuitry must be transmitted to the environment
effectively, lest the chip temperature rise disastrously.
In material terms, the electrical signal paths require high-conductivity
metals (e.g , copper, aluminum, gold) and low-dielectric-constant insulation
materials (e.g., polyimides, epoxies, hydrocarbons, and fluorinated polymers).
The speed of light is a practical limiting factor in advanced circuits. For
power delivery, high-conductivity metals are again necessary, but high
capacitance that is physically close (i.e., low impedance) to the chip
requires high-dielectric-constant capacitor materials, usually ceramic.
Thermal conductivity favors metal, whereas other ceramic paths and polymers
are thermal insulators. Thermal coefficient of expansion (ICE) is a critical
factor in package design. Silicon has a low ICE compared with common metals
and organic polymers. Thus, mechanical stresses are created when temperature
changes occur as in manufacture, temperature-cycle testing, and use. The
problem becomes more difficult as chip size increases. Thinner sections of
the molded body are more susceptible to thermal-mechanically induced cracking
failure. ICE of polymeric materials can be controlled by the addition of low-
TCE fillers, as is conventional for molding compounds and printed wiring board
19
resins. Many packaging and interconnection materials are composites designed
to improve the TCE match.
As electronic equipment density increases, power dissipation becomes an
ever greater problem. In general, heat is conducted away from the chips by
the thermal conductivity of the materials employed. Metals and ceramics are
relatively good thermal conductors, but polymeric materials as a class are
poor conductors, a factor that will assume greater importance over the next
few years. The tradeoff of dielectric constant and thermal conductivity will
have to be met by compromises between materials and physical design.
Application of fluid heat-exchange media will also increase, but the cost of
this option is high, therefore, integration of this approach into physical
design is essential. Thermoelectric cooling offers an alternative to thermal
conductivty, a technology that has been applied to some commercial circuits.
This report begins with a discussion of system trends and needs (Chapter
2), followed by a description of approaches that have been employed for
packaging and an indication of current trends (Chapter 3~. Chapter 4
discusses materials issues, and Chapter 5 gives more specific information and
perspective on plastic and ceramic encapsulants, ceramic substrates, and
organic printed circuit structures. Chapter 6 presents an analysis of
material sources, current trends, and the importance of the field in the
context of international competitiveness. These discussions lay the
for future actions in terms of specific
technical development and research, and the organizational and political
factors that distinguish the United States from other countries.
Groundwork for the recommended ens ~ ^
his cus s ions lay
in terms of
