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Ultra Lame Scale Integration and Beyond JAMES D. MEINDL The objective of this paper is to project the future of integrated electronics by studying the theoretical, practical, and analogical limits that govern its progress. The limits governing ultra large scale integration (ULSI) of 10 million to 1 billion transistors in a single chip of silicon (Si) can be organized in a hierarchical matrix, as illustrated in Figure 1. At the first level of the hierarchy are fundamental limits, which are immutable laws of nature; they cannot be changed. At the second level are material limits, which are specific to composition but do not change frequently in practice. Silicon has been the keystone material of inte- grated electronics for the past two decades, and this is unlikely to change during the next two. At the third level, device limits depend upon both the material properties and configuration of ULSI components. Con- sequently, these limits are useful in projecting the smallest possible dimensions of structures such as insulated gate field effect transistors (IGFETs). At the fourth level are circuit limits unique because they retain both a complete physical description and a definition of the in- formation-processing function of a group of components and intercon- nections. Moreover, circuit limits describe device performance in a re- alistic operating environment, not in sterile isolation. Consequently, the circuit level of the hierarchy is the most appropriate one for projecting the smallest allowable dimensions of ULSI structures for specific pur- poses. The fifth level, the system limits, can be elaborated into several discrete steps reflecting the logic design, architecture, instruction set, 5

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6 COMPUTERS OF THE FUTURE THEORETICAL PRACTICAL ANALO GICAL 5. SYSTEM 4. CIRCUIT 3. DEVICE 2. MATERIAL 1. FUNDAMENTAL FIGURE 1 Hierarchical matrix of limits governing integrated elec- tronics. algorithms, and application of a particular ULSI configuration. System limits are the most numerous and nebulous set of the hierarchy. How- ever, because opportunities for integration at each of the five hierar- chical levels are constrained by the limits of all preceding levels, system limits represent the most profoundly important set. As will be discussed in the next two major sections of this paper, both theoretical and practical limits are included at each level of the hierarchy. For example, at the fundamental level thermal fluctuations impose a theoretical limit on switching energy of several kT (where k is Boltz- mann's constant and T is absolute temperature) that is further restricted by practical constraints on cooling temperature. With regard to the second, or materials, level, although theory suggests use of high-mobility GaAs or InP materials, for overwhelming practical reasons Si dominates integrated electronics. At the third level, avoidance of drain-to-source junction punch-through determines a theoretical minimum channel length for IGFET devices that may never become practical because of man- ufacturing limitations of microlithographic technology. At the fourth level, practical supply voltage standards may prevent reaching theoret- ical circuit limits on the power-delay product of complementary metal- oxide-semiconductor (CMOS) technology. And, finally, common clock skew illustrates a simple system limit depending on interconnect time delay. The totality of practical limits is described by three parameters that collectively measure the overall rate of progress of integrated electron- ics: (1) minimum feature size, (2) die area, and (3) packing efficiency of a complex chip. Packing efficiency has been described by Moorer as "cleverness." Its precise definition is the number of transistors per min- imum feature area. The combined time derivatives of these parameters determine the rate of change of the total number of components per chip, the central measure of progress in integrated electronics.

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ULTRA LARGE SCALE INTEGRATION AND BEYOND . 7 As discussed in the section on analogical limits, an intriguing projec- t~on of the long-term future of integrated electronics can be developed by comparison of the mature industrial revolution with the modern information revolution. A correspondence between structural materials in the industrial revolution and electronic materials in the information revolution suggests a set of long-term analogical limits on ULSI. The observation that technological advances in different fields often have followed similar patterns of development provides a basis for introducing these limits. THEORETICAL LIMITS This section projects the smallest allowable dimensions for integrated structures using as relevant criteria circuit limits associated with IGFETs, polycrystalline silicon or polysilicon resistors, and interconnections. Transistors Fundamental, material, and device limits in digital electronics have been surveyed by Keyes.2 Dennard et al.3 described a constant electric field scaling theory for IGFETs. A later publications discussed constant voltage and quasi-constant voltage scaling. Most recently, experimental IGFETs with effective channel lengths of approximately 0.15 microns were reported by Fichtner et al.5 Constant electric field (CE) scaling of IGFETs begins with the defi- nition of a device scaling factor S > 1. All lateral and vertical device dimensions are scaled down by the same factor 1/S. In addition, drain supply voltage is scaled as 1/S in order to maintain a constant electric field intensity and consequently undiminished safety margins for device operation. The principal benefits of CE scaling are a device delay time that decreases as 1/S, a power density that remains constant, a packing density that increases as S2, and a power-delay product that decreases as 1/S3. In comparison, constant voltage (CV) scaling also calls for reducing device dimensions by the factor 1/S, but supply voltage remains constant in order to maintain compatibility with established standards. The prin- cipal benefits of constant voltage scaling are device delay time, packing density, and power-delay product that scale as 1/S2, S2, and 1/S, re- spectively. A disadvantage of CV scaling is a power density that increases as S3 and therefore aggravates the already serious heat-removal problem in integrated electronics. In practice, a compromise between CE and

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8 COMPUTERS OF THE FUTURE CV scaling (roughly equivalent to quasi-constant voltage [QCV] scaling) has prevailed and can be expected to continue. This compromise includes scaling different dimensions at different rates. At this time the state-of-the-art minimum feature size of commercial very large scale integration (VLSI) is approximately 2.0 microns. It is pertinent to ask, "Can we project future ULSI structures with 0.2 micron minimum feature sizes?"6 To respond on the basis of circuit scaling limits, an accurate analytical circuit model for short-channel IGFETs offers marked advantages in physical insight and computational effi- ciency in comparison with empirical or numerical models. An early IGFET circuit models described long-channel superthreshold device be- havior. It was extended to describe subthreshold performances and the coarse effects of short channels via geometric charge sharing approxi- mations.9 Recent models based upon analytical solution of the two- dimensional (2D) Poisson equations ~~ effectively account for short- channel and source/drain bias effects. Although these 2D models lack the high accuracy of CAD models of current state-of-the-art IGFETs,~2 their compact representation of 2D effects provides a promising basis for investigation of integrated circuit limits. The 2D models have been employed in studies of enhancement/depletion N-channel MOS transis- tor (E/D NMOS) and N-channel and P-channel or complementary MOS transistor (CMOS)~i digital circuits. For conservative design margins, typical results suggest that IGFET channel lengths can be reduced to approximately 0.40 microns in E/D NMOS logic gates, 0.30 microns in CMOS transmission gates, and 0.20 microns in CMC,S logic gates. Smaller channel lengths can be projected for more aggressive designs. The dom- inant mechanism imposing these limits is subthreshold drain current or leakage current, which degrades integrated circuit performance and thereby forces an end to IGFET scaling. Resistors Following the pattern of CE IGFET scaling, resistor scaling calls for reducing all device dimensions by the factor 1/S. Since both voltage and current scale as 1/S, resistance remains constant. Consequently, resis- tivity must decrease as 1/S for CE scaling. (For CV scaling, resistance decreases as 1/S and resistivity as 1/S2.) Because of its advantages in static random-access memory chips, or SRAMs, polysilicon is now the most widely used resistor material in VLSI. Scaling polysilicon resistivity is enhanced by recent advances in modeling carrier transport in this material.~3~~5 Salient features of ad- vanced models include identical cubic grain sizes, uniform ionized im-

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ULTRA LARGE SCALE INTEGRA TION AND BEYOND 9 purity distribution without segregation at grain boundaries, monoener- getic interface traps, symmetrical semiconductor-to-semiconductor ab- rupt junctions at grain interfaces, thermionic emission over barriers for T ~ 27C, one-dimensional carrier transport, equally distributed voltage increments across grains, and partially or totally depleted grains. Con- sidering both bulk crystallite and grain boundary contributions to resis- tivity yields a sinh current-voltage characteristic whose argument varies inversely with the number of grains in the resistor. Hence, linearity is enhanced as the number of grains increases or as the voltage increment per grain decreases. In addition, measurements indicate that the sen- sitivity of resistivity to fluctuations in doping concentration is inversely related to crystallite size. The implications of the two preceding properties in terms of resistor scaling are unfavorable. Scaling length by 1/S requires reducing voltage by 1/S in order to maintain the same degree of linearity and reducing the number of grains by 1/S to prevent sensitivity degradation. Thus, QCV scaling tends to degrade linearity, and the small numbers of grains encountered at submicron lengths imply large variances in distributions of resistance values. The unfavorable consequences of scaling polysilicon resistors to lengths smaller than 1.0 micron suggest their replacement with silicon-on-insulator (SOI) transistors fabricated in polysiliconi6 or recrystallized silicon.~7 Interconnections Scaling of interconnections entails the definition of both a device scaling factor S and a chip scaling factor Sc > 1, since die area tends to increase with time. Again following the pattern of CE scaling, local interconnections (e.g., interconnections within a logic gate or between adjacent gates) are scaled in all dimensions by 1/S. However, long- distance interconnections (e.g., interconnections extending from corner to corner of a die) are scaled by Sc in length and 1/S2 in cross-sectional area. Among the results of local interconnect scaling (in combination with CE IGFET scaling) are that the interconnect time constant or response time and voltage drop remain constant and current density increases with S. Since IGFET time delay decreases as 1/S, a constant local interconnect response time assumes increasing importance. More- over, the salient result of long-distance interconnect scaling is a response time that increases rapidly as (SSc)2.~9 Long-distance interconnections fabricated with polysilicon or silicide materials now exhibit response times well in excess of individual logic gates. If current trends persist, even aluminum interconnects will surpass logic gates in response time

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10 COMPUTERS OF THE FUTURE during the mid-1980s. To push back this barrier, greater use of multilevel metal interconnections can reduce average interconnect length.20 In ad- dition, cascade line drivers and repeaters are useful circuit techniques. A key design criterion is that total interconnect resistance should be less than about 2.3 times the driver transistor resistance. New chip architectures that reduce average interconnect length represent a prom- ising approach at the system level. Although the preceding discussion of interconnect scaling applies spe- cifically for line-to-substrate parasitic capacitance in combination with CE IGFET scaling, the salient results remain largely unaltered as one Extends the analysis to include line-to-line parasitic capacitance, CV IGFET scaling, and scaling different dimensions (e.g., interconnect thickness and field insulator thickness) at different rates.2i Overview A representative overview of the hierarchy of limits governing inte- grated electronics is obtained by a power-delay plot, as illustrated in Figure 2. The fundamental limits are due to thermal noise and the quantum mechanical uncertainty principle. The material limit on carrier lo-2 - '-3 -4 10 10-d 10 I`J 10 6 o lo-8 10 1.0 fJ 10-7 _ AMATERIAL-. 1.0pJ lOnJ "N " " : ' " '. DEVICE CIRCUIT 2~ As T> Lmin ~~ ~i2D it' ~ lo-lo lo-14 10-13 10-12 10-11 10-10 10-9 10 8 10 10 10 T. DELAY, lsec] FIGURE 2 Hierarchy of limits illustrated in power-time delay plane including fundamental limits from thermodynamics (4kT/~) and quan- tum mechanics (him) as well as material, device, and circuit limits. The dotted line represents 1982 state-of-the-art circuitry.

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ULTRA LARGE SCALE INTEGRA TION AND BEYOND 11 transit time in Si is imposed by scattering limited carrier velocity and critical field strength. The IGFET device limit is set by velocity satu- ration and punch-through. The circuit limit applies to a CMOS logic gate with minimum-geometry IGFETs. The dotted line in Figure 2 rep- resents the state-of-the-art power-delay product circa 1982. PRACTICAL LIMITS Theoretical limits are based on the principles of solid-state science, whereas practical limits depend on manufacturing processes and equip- ment. The status of the five levels of practical limits that constrain integrated electronics can be summarized in terms of three parameters: minimum feature size, die area, and packing efficiency. Although the- oretical studies have established limits on minimum feature size, similar limits on die area and packing efficiency have not been defined. Feature Size During the period 1959 to 1975 minimum feature size decreased at a rate of approximately 11 percent per year, resulting in a halving every six years.) (Minimum feature size is defined as one-half the minimum pitch, or the average of minimum line width and spacing.) A 50 percent reduction in feature size over six years corresponds to a 4-times increase in components per unit area. In turn, this equates to approximately an 8.7-times increase in components per unit area per decade. Since 1975, minimum feature size has continued to shrink at its previous rate, reach- ing a value of approximately 2.0 microns in 1982 in state-of-the-art commercial integrated electronics. It has been estimated that optical lithography, the primary tool for wafer exposure, will reach the limits of its capacity for small feature sizes in the range of 0.75 to 0.50 microns.22 23 Assuming that feature size continues to decrease at its historical rate, optical lithography as practiced in widespread high-volume production should reach its limits in the 1990-1994 period. In this range of time a breakpoint in the feature size versus time curve followed by a reduction in slope may be anticipated. Thereafter, more advanced microlitho- graphic techniques such as E-beams and X-rays should extend IGFET minimum feature size to its theoretical limits in the 0.40- to 0.20-micron range (Figure 34. Die Size From 1959 to 1975 integrated circuit die area increased at a rate of approximately 9 percent per year, resulting in a quadrupling of die area

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12 COMPUTERS OF THE FUTURE and a doubling of the associated die edge every eight years.) Since 1975, die area has continued to grow at approximately its previous rate (Figure 4), reaching a "representative range" of about 36 to 64 square milli- meters (mm2) in 1982, depending on the type of circuit, including pro- grammable read-only memories (PROMs), electronically programmable read-only memories (EPROMs), static random-access memories (SRAMs), dynamic random-access memories (DRAMs), microcom- puters, image sensors, and gate arrays, within the estimate. A 100 percent increase in die edge over eight years corresponds to a 4-times increase in components per chip and therefore approximately a 5.7-times increase in components per chip per decade. From 1959 to 1982 the combined effects of decreasing minimum feature size and in- creasing die size produced an increase of approximately 49 times per decade in the number of components per chip. In projecting future increases in die size, it is assumed that the his- torical rate established through optical lithography will continue into the early 1990s. Thereafter, the combined effects of decreasing minimum feature size and increasing die size (i.e., the combined effects of further advances in lithography) might be expected to produce an increase of about 5 times per decade in the number of components per chip. Several arguments can be suggested for this projected 10-times falloff in litho- ~ 100 c o E - N An F \ 111 Ct ID lL Z. 1.0 '" a: a: "S" \ 0.1 1960 1970 - a. I I I A, 1980 1990 2000 2010 CALENDAR YE AR FIGURE 3 Average minimum feature size versus calendar year.

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ULTRA LARGE SCALE INTEGRA TION AND BEYOND D 00 - 111 a: a: 10 I ''Sc' 1 ~ 1960 / ,' .' 1970 1980 1990 CALE NDAR YE AR FIGURE 4 Die edge versus calendar year. 13 2000 2010 graphic productivity increases. The proximity of the theoretical limits on minimum feature sizes will slow advances in ULSI technology. New and more demanding lithographic techniques such as E-beams and X- rays will be necessary to surpass the limits of optics. More severe pack- aging problems, including interconnections and heat removal, will in- hibit die size. Finally, experience already has shown a drastic reduction in the rate of increase of packing efficiency, thus suggesting the possi- bility of a similar rate reduction due to lithography. Recent advances in the use of redundancy in large memory chips offer promise of developments in wafer scale integration (WSI) that will de- part markedly from historic trends in die size. Although the future course of these efforts has not been projected, one may speculate on a step increase of more than 10 times in monolithic silicon substrate area, compared with the area of a single die, for future integrated systems incorporating wafer scale integration. Packing Efficiency The contribution of process, device, and circuit innovations to in- creasing the number of components per chip can be described by a packing efficiency parameter. To compute a representative value of this contribution, for example, suppose that a 256K DRAM cell occupies an area of 71 square microns with a minimum feature size of 1.5 microns. Moreover, suppose a preceding 65K DRAM cell occupies an area of 256 square microns with a minimum feature size of 2.0 microns.

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14 10 : _ : _ HE 1O-1 _ a _ cot' . z LL 2 LL z y 10-3 1960 1970 1980 1990 2000 2010 (PE) - - _ _ _ _ _ _ - - (PE) CALENDAR YEAR FIGURE 5 Packing efficiency versus calendar year. COMPUTERS OF THE FUTURE 10 lol 2 103 The resulting packing efficiency contribution can be computed as (256/714~1.5/2.042 = 2.03 times. An alternative approach is to observe, for example, that the overall rate of increase of components per chip is 102 times per decade and that the combined contributions of decreasing feature size and increasing die size account for 49 times per decade, thus giving 2.1 times per decade as the packing efficiency contribution. A plot of packing efficiency versus calendar year indicates that about an order-of-magnitude reduction in its rate of increase occurred in the early 1970s (Figure 5~. Number of Components per Chip From 1959 to 1972/1973 the total number of components per chip increased from 1 to approximately 11,000. This corresponds approxi- mately to an increase of 100 percent annually, or 1,024 times per decade. Given that smaller minimum feature sizes and larger die sizes accounted for 8.7- and 5.7-times-per-decade increases, respectively, packing effi- ciency improvements must then have produced about a 21-times-per- decade increase in the number of components per chip. From 1972/1973 to 1981 the number of components per chip increased from approximately 11,000 to 600,000 (e.g., the 256K DRAM) corre- sponding to an increase of 59 percent per year, 4 times per three years,

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UL TRA LARGE SCALE INTEGRA TION AND BEYOND 15 or 102 times per decade. Since smaller feature sizes and larger die sizes continued to account for 8.7- and 5.7-times-per-decade increases, re- spectively, during this period packing efficiency improvements produced only a 2.1-times-per-decade increase in the number of components per chip. This drastic reduction of 10 times in the rate of packing efficiency improvements apparently is the result of exhausting relatively easily obtained gains in layout density that marked the first decade or so of integrated electronics. The packing efficiency contribution of about 2.1 times per decade achieved since 1972/1973 may be maintained through the 1980s and perhaps the l990s as well. Advances in multilevel (sometimes referred to as three-dimensional, or 3D) integrated circuits will contribute to this advance. However, the problems of wafer scale integration appear to be more readily amenable to solution, e.g., through the use of redun- dancy, than do those of multilevel circuits with more than two levels of active devices. Thus, assuming that the problems of product definition and design as well as of heat removal24 are solved, wafer scale integration may become the source of a new factor increasing the number of com- ponents per monolithic Si substrate. Overview i1 An overview of the preceding discussion of practical limits is illustrated n Figure 6. The projected lower boundary corresponding to line segment E assumes a 0.75-micron limit for optical lithography and a 0.50-micron limit for IGFET minimum feature size. The upper boundary corre- sponding to D assumes a 0.50-micron limit on optical lithography and a 0.25-micron limit for IGFETs. The expected range of performance lies within these boundaries. ANALOGICAL LIMITS Historical studies indicate that technological advances in different fields often follow similar patterns of development. For example, it has been observed that a growth curve that follows an S shape (a slow start, then a rapid rise, followed by a leveling off and obsolescence) is a common pattern.25 26 This has led to the use of historical analogy as a forecasting tool. An analogy between structural materials in the indus- trial revolution and electronic materials in the information revolution can be formulated as a guide to long-term expectations in ULSI. The dominant chemical element of the industrial revolution has been iron (Fe). Silicon occupies a similar position in the information revo-

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16 107 VLSI 10 10 LSI lO 103 MSI SSI lO _ - llJ AL 2 _ Z Z o o ZSI-10 1960 1970 COMPUTERS OF THE FUTURE // ?C,~' DRAM ~ _ X ARC ~ /B o o o WSI 0 ,~.'' ??? F ,,. '7? E 10~ GSI 109 - 10 ULSI CALENDAR YEAR VLSI FIGURE 6 Components per chip versus calendar year. Segments A and B are history. Segments C, D, E, F. and G are projections. E F assumes 0.75-micron limit on optical lithography and 0.5-micron limit on IGFET minimum feature size. D G assumes 0.50- micron limit on optical lithography and 0.25-micron limit on IGFET minimum feature size. lution.27 An Fe/Si analogy can be extended hierarchically to compounds, components, and systems. By alloying carbon (C) and other elements such as chromium (Cr) and nickel (Ni) with Fe, special-purpose steel ingots can be cast. In analogous fashion, boron (B), phosphorus (P), or antimony (Sb) dopant is added to Si to prepare single-crystal ingots for various discrete devices or integrated circuits. Engine blocks and pistons are examples of specialized steel components corresponding to IGFET and bipolar integrated circuits intended for different purposes. Finally, automobiles, skyscrapers, and railroads represent the steel systems of the industrial revolution as portable computers, mainframes, and com- munications networks mark the silicon systems of the information rev- olution. The principal technical figure of merit of structural materials is their strength-to-weight ratio. For electronic materials and devices, the re- ciprocal power-delay product is the most useful figure of merit. In ap- plications such as high-speed aircraft where the strength-to-weight ratio of steel has been found wanting, aluminum (Al) has been a valuable replacement. For high-speed electronic circuits where Si devices are too

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UL TRA LARGE SCALE INTEGRA TION AND BEYOND 17 slow, GaAs technology has prevailed, thus suggesting a second struc- tural/electronic materials analogue. In the most demanding applications, such as jet engines, where the largest possible strength-to-weight ratios are required at very high temperatures, aircraft engine designers have selected titanium (Ti) as the appropriate structural material. A corre- sponding position is occupied by superconductive devices that offer the largest reciprocal power-delay product of all currently known electronic technologies. Moreover, the impact of superconductive devices on the information revolution is yet to come. For several decades various types of plastics have served remarkably well as low-cost, lightweight, and in many instances superior-performing replacements for structural metal alloys. Current research to develop semiconductor-on-insulator materials (particularly Si) for integrated electronics is aimed at an analogous set of targets that again represent potential future advances. Finally, the most exotic or largest strength- to-weight ratio structural materials now in use are composites in which crystalline fibers of C, B. or glass, for example, are embedded in a host or binding material. Future multimaterial wafers such as Si-Ge-GaAs- GaAlAs structures, perhaps fabricated by molecular beam epitaxy, can be conceived as the counterparts of structural composites. Extension of this set of analogies will be left to the imagination of the reader (e.g., consider germanium Agent. Annual production in tons of steel, aluminum, titanium, and plastics in the United States since 1860 is summarized in Figure 7. The figure also illustrates estimated annual world and U.S. production of single- crystal silicon and world production of all other single-crystal electronic materials in equivalent square inches of wafers. It is interesting to ob- serve that the rate of steel production in the United States doubled every two years from 1860 through about 1910. For more than the past decade Si has followed the same trend. Another remarkable feature of the data is that after more than a century of high-volume production, steel re- mains the dominant structural material. Moreover, the history of Al, Ti, and plastic suggests a myriad of exciting future material, device, and circuit advances to propel the information revolution. The possibility that the future course of electronic materials may follow the historic patterns of structural materials implies an intriguing set of long-term analogical limits on integrated electronics. CONCLUSION The rate of progress toward the hierarchy of limits governing inte- grated electronics was extremely rapid during the 1960s and early 1970s.

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18 x 106 tons 3: 2 101 _ 100 _ 10 11 _ 1o2 to3 t85060 70 80 901900 10 20 3040195060 70 80 90 2000 /~oK'l/\l lo/ / / ill, 1'' 0 / / // / x /'xti x COMPUTERS OF THE FUTURE / / TO arbor O 0 o STEEL PLASTIC ALUMINUM ~~ x / x~ 43 x x ~ I\/ x SILICON OrlbFr_ TITANIUM ' 1~/ m-~+ i , , , , , , , , , , , ~ , , , in2 109 loo J1o7 _ lo6 FIGURE 7 Structural and single-crystal electronic materials production in the United States and the world (T) versus calendar year. . A perceptible decrease in this rate has been observed since the mid- 1970s and is projected to continue until the early l990s. Theoretical limits on minimum feature size and practical limits on lithography and reliability predict a further rate reduction at that time. Nevertheless, as illustrated in Figure 6, chips incorporating several hundred million to a billion (i.e., gigascale integration, or GSI) components are anticipated by the year 2000.28 29 Following this, analogical limits suggest a continued high level of utilization of silicon integrated electronics as well as rapid advances and volume applications of complementary technologies. Al- though these projections are quite encouraging, they are limited to extrapolation of already identified trends. The possibility of fundamen- tally new discoveries and inventions can only add to future prospects.

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ULTRA LARGE SCALE INTEGRA TION AND BEYOND NOTES 19 1. G.E. Moore, "Progress in Digital Integrated Electronics," Tech. Dig., 1975 IEEE IEDM, pp. 11-13. 2. R.W. Keyes, "Physical Limits in Digital Electronics," Proc. IEEE, 63:740-767, May 1975. 3. R.W. Dennard et al., "Design of Ion Implanted MOSFET's With Very Small Physical Dimensions," IEEE JSSC, SC-9:256-268, Oct. 1974. 4. VLSI Lab, Texas Instruments Inc., "Technology and Design Challenges of MOS VLSI," IEEE JSSC, SC-17:442-448, June 1982. 5. W. Fichtner et al., "0.15 ,um Channel-Length MOSFETs Fabricated Using E-Beam Lithography," IEEE ED Lett., EDL-3:412-414, Dec. 1982. 6. G.E. Smith, "Sub-micron NMOS Technology for High Speed VLSI," 1983 Symp. on VLSI Tech., Digest, pp. 102-103, Sept. 1983. 7. H. Ihantola and J. Moll, "Design Theory of a Surface Field Effect Transistor," Solid- State Electron., 7:423-430, 1964. 8. R.M. Swanson et al., "Ion-Implanted Complementary MOS Transistors in Low- voltage Circuits," IEEE JSSC, SC-7:146-153, Apr. 1972. 9. L.D. Yau, "A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET's," Solid-State Electron., 17:1059-1063, 1974. 10. K.N. Ratnakumar et al., "Short-Channel MOST Threshold Voltage Model," IEEE JSSC, SC-1 7:937-947, Oct. 1982. 11. J.R. Pfiester et al., "Performance Limits of NMOS and CMOS," IEEE ISSCC Tech. Dig., pp. 158-159, Feb. 1984. 12. H.I. Hanafi et al., "An Accurate and Simple MOSFET Model for Computer-Aided Design," IEEE JSSC, SC-17:882-891, Oct. 1982. 13. J.Y.W. Seto, "The Electrical Properties of Polycrystalline Silicon Films," J. Appl. Phys., 46:5245-5254, 1975. 14. N.C.C. Lu et al., "Scaling Limitations of Monolithic Polycrystalline-Silicon Resistors in VLSI Static RAM's and Logic," IEEE JSSC, SC-17:312-320, Apr. 1982. 15. N.C.C. Lu et al., "High Field Conduction Mechanisms in Polycrystalline Si Resistors," Tech. Dig., 1982 IEEE IEDM, pp. 781-785. 16. T. Kamins, "MOS Transistors in Beam Recrystallized Polysilicon," Tech. Dig., 1982 IEEE IEDM, pp. 420-424. 17. J.F. Gibbons et al., "A Folding Principle for Generating 3-D MOSFET's in Beam- Recrystallized Polysilicon Films," Tech. Dig., 1982 IEEE IEDM, pp. 111-114. 18. K.C. Saraswat et al., "Effect of Scaling of Interconnections on the Time Delay of VLSI Circuits," IEEE JSSC, SC-17:275-280, Apr. 1982. 19. J.D. Meindl et al., "Circuit Scaling Limits for Ultra-Large Scale Integration," Digest, 1981, IEEE ISSCC, pp. 72-73. 20. P.E. Cottrell et al., "Multidimensional Simulation of VLSI Wiring Capacitance," Tech. Dig., 1982 IEEE IEDM, pp. 548-551. 21. H.B. Bakoglu et al., "Optimal Interconnect Circuits for VLSI," IEEE ISSCC Tech. Dig., pp. 164-165, Feb. 1984. 22. A.N. Broers, "Resolution, Overlay and Field Size for Lithography Systems," IEEE ED, ED-28:1268-1281, Nov. 1981. 23. J.H. Bruning, "Optical Imaging for Microfabrication," Semicond. Int., pp. 137-156, Apr. 1981. 24. D.B. Tuckerman et al., "High Performance Heat Sinking for VLSI," IEEE ED Lett., EDL-2:126-129, May 1981. 25. J.P. Martino, ea., An Introduction to Technological Forecasting, Gordon & Breach, New York, pp. 13-25, 1972.

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20 COMPUTERS OF THE FUTURE 26. O.G. Folberth et al., "The Fundamental Limitations of Digital Semiconductor Tech- nology," Microelectron. J., 9:33-41, 1979. 27. J.D. Meindl, "VLSI and Beyond,'' Keynote address at Microelectronica 1982, Ein- dhoven, The Netherlands, Jan. 1982. 28. R.W. Keyes, "The Evolution of Digital Electronics Towards VLSI," IEEE ED, ED- 26:271-279, Apr. 1979. 29. J.D. Meindl, "Theoretical, Practical and Analogical Limits in ULSI," Tech. Dig., 1983 IEEE IEDM, pp. 8-13.