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4 Generic Technical Issues Associated with Materials for High-Temperature Semiconductors For the high-temperature semiconductors being considered in this report, process technologies must be assessed in addition to performance effectiveness. The existence of processing technology that is compatible with high-quality materials will determine whether a device and circuit technology can be built from these materials. This chapter discusses the most important materials- dependent processing technologies required for the production of high-temperature semiconductors. The following issues are considered: (1) electrical contacts, (2) doping and implantation, (3) gate oxides and insulators, (4) etching, (5) defect engineering and control, (6) yield, and (7) device reliability. The committee expects more focus on these areas as the high-temperature device technologies mature and as more long-term reliability studies at elevated temperatures take place. ELECTRICAL CONTACTS The requirements for high-quality contacts for high- temperature electronic devices are similar to their low- temperature counterparts, but these contacts may be more prone to degradation at their elevated temperatures of operation. Therefore, studies on the mechanisms of intermetallic and metal semiconductor reactions, interdiffusion reactions, and electrical changes as a function of time will be critical to projecting device stability and reliability. Finding a means of forming effective, reliable contacts to high-temperature semiconductors will obviously have important consequences to other device applications of these wide bandgap materials. This section focuses on ohmic contacts to SiC and GaN, and Schottky contacts to SiC. Of the wide bandgap semiconductors, research in electrical contacts to these 39 materials is currently the most mature. Although progress with GaN has been encouraging, ohmic contacts with low contact resistance remains a significant issue that needs to be addressed for the nitrides and diamond. Some of the high-temperature metallization issues for ohmic contacts are addressed since the initial choices of metals must begin by addressing the high-temperature issues. Extensive testing and stressing at high temperatures is only in initial stages, however. Schottky Contacts to SiC Most transition metals form good Schottky contacts on e-type (or- and a-) and p-type (a-) SiC with Schottky barrier heights (SBHs) typically greater than or equal to 1 eV. Positive correlations that were less than 1 eV between the SBHs and work functions of several metals were found in a number of studies (Waldrop et al., 1992; Porter et al., 1993, 1995a, b; Waldrop and Grant, 19931. These results indicate a partial pinning of the Fermi level in SiC. Low leakage currents at room temperature for contacts on both n- and p-type 6H-SiC have been common, while the characteristics of contacts on JI-SiC films have been very dependent on the quality (i.e., defect density) of the B-SiC films. Breakdown voltages greater than 1,100 V for gold diodes on the carbon-terminated surface (Urushidani et al., 1993) of e-type 6H-SiC have been achieved. Recently, Schottky diodes in pre- production packaging have been demonstrated with breakdown voltages greater than 1,200 V. Ohmic Contacts to SiC The combination of the wide bandgap and surface states in SiC make the fabrication of ohmic contacts to this material, especially p-type SiC, exceptionally difficult

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Materials for High-Temperature Semiconductor Devices TABLE 4-1 Selected Ohmic Contacts to e-Type 6H-SiC and Measured Contact Resistivities at Room Temperature Contact Carrier Concentration Annealing Contact Resistivity Metallization (cm~3) in 6H-SiC Conditions (Q cud) Reference TiW 4.7 x 10~8 600 C/5 min 7.8 x 104 Crofton et al., 1991 Titanium 1 x 102 none <2 x 10-5 Alok et al., 1993 Nickel 7-9 x 10~8 950 C/2 min <9 x 10-6 Crofton et al., 1994 Ni/3C-SiC 1-2 x 10~8 1000 C/30 s 1.7-6 x 10-5 Dimitriev et al., 1994 SOURCE: Porter et al. (199Sb). to achieve. Most ohmic contacts rely on high doping concentrations in the SiC and must be annealed at temperatures between 800 C and 1300 C (Porter et al., 1995a, b). Tables 4-1 and 4-2 list selected ohmic contact metallizations and their corresponding contact resistivities on n- and p-type 6H-SiC, respectively. Additional ohmic contacts are shown in Table 4-3. Annealed nickel and aluminum have been the most common ohmic contact metallizations for n- and p-type (ax- and B-) SiC, respectively. Because of the very high thermodynamic driving force for oxidation of aluminum, annealing aluminum, or aluminum alloys can result in the formation of an insulating oxide layer. The fabrication of ohmic contacts that have low contact resistivities ~ < 10-s Q cm2) and are thermally stable on SiC will be one of the most critical issues for the advancement of SiC devices. In addition to reducing the Schottky barrier, the reactions at the metal/SiC interface and their kinetics must be considered if SiC devices are to be operated at high temperatures. Ohmic Contacts to GaN Table 4-4 summarizes some of the state-of-the-art contacts made to GaN. Generally, good ohmic contacts have been made to both n- and p-type GaN. SBHs are found to be dependent on the metallic work function, indicating that the surface Fermi energy of GaN is unpinned, in contrast to both SiC and ZnSe (and most other compound semiconductors). Morl~oc et al. (1994) speculates on the nature of the low-resistance contacts to GaN Two possible mechanisms for low-resistance 40 contacts are discussed: low-barrier Schottky contacts coupled with intermediate or graded bandgap interfaces and tunneling. DOPING AND IMPLANTATION Finding suitable shallow dopants for large bandgap semiconductors is one of the major limitations to the development of these materials for device applications. Doping has been achieved by co-deposition during growth of the film itself, or by ion implantation. Both of these technologies have been employed for all the large bandgap semiconductor materials with greater or lesser success, depending on the particular system. Diffusion doping has been attempted in some cases, but this approach has been found to be unacceptable for device fabrication. Doping to achieve both n- and p-type materials in SiC has been shown to be easier, for example, than in either GaN or ZnSe. For SiC, nitrogen has been predominantly used as the e-type dopant, while aluminum is generally used as the p-type dopant. With respect to doping by implantation, SiC, particularly 6H-SiC, has been the most widely studied of all large bandgap semiconductor materials. Methods for both n- and p-type doping of Group III nitrides are required. As improved quality materials become available in GaN and A1N, similar studies are anticipated. Doping of SiC Nitrogen is the most frequently used e-type impurity, while aluminum is most common for p-type doping in

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Generic Technical Issues Associated with Materials for High-Temperature Semiconductors TABLE 4-2 Selected Ohmic Contacts to p-Type 6H-SiC and Measured Contact Resistivities at Room Temperature Contact Carrier Concentration Annealing Contact Resistivity Metallization (cm~3) in 6H-SiC Conditions (Q cm2) Reference Aluminum 1.8 x 10~8 700 C/10 min. 1.7 x 10-3 Crofton et al. 1991 Al-Ti 2 x 10~9 1000 C/5 min. 1.5 x 10-5 Crofton et al., 1993 Al/3C-SiC not reported 950 C/2 min. 2-3 x 10-5 Dimitriev et al. 1994 SOURCE: Porter et al. (199Sb). CVD (chemical vapor deposition). Dopants may be introduced either during epitaxy or later using ion implantation. For CVD, nitrogen and triethylaluminum (TEA) have proven to be suitable dopant source gases for n- and p-type doping, respectively. When e-doping is introduced during growth, carrier concentrations as high as ~ x 10~9 cm~3 can be realized. Ion implantation with subsequent argon annealing has yielded electron concentrations as high as 3 x 10~9 cm~3 at an e-dose of 5 x 102 cm~3 (D.M. Brown et al., 1994; Clarke et al., 1993). Acceptor, p-type doping is a recognized problem in SiC, although considerable progress has been made. All of the acceptor impurities thus far investigated, namely aluminum, boron, gallium, and scandium, form deep levels, are difficult to activate, and generally require a high-temperature anneal. The depth of the acceptor levels also leads to the hole concentration varying quite strongly with respect to temperature, considerably complicating device design and operation. Aluminum is somewhat difficult to incorporate into the SiC lattice and high carrier concentrations are difficult to achieve. Researchers at Kyoto University have obtained p-type carrier concentrations in the 10~9 to 102 cm~3 range, using TEA in a CVD process on the silicon face of 6H-SiC. In contrast, growth on the carbon [ace permitted only 2 x 10~8 cm~3 p-type doping. The carrier concentration could be easily controlled down to the low p = 10~6 cm~3 range. On the upper end, the observed hole concentration became nonlinear as a function of TEA flow above 10~9 cm~3 In general, [background nitrogen causes unintentionally doped crystals to be e-type. In the best 6H-SiC samples ( < colt cm~~ nitrogens, background carrier concentrations , _, ~1A ~. 41 in the mid-10'4 cm~3 range have been achieved. Further improvements should be possible as sources of nitrogen contamination are eliminated. A review of the optical and electrical properties of doped SiC has been published by Pensl and Choyke (1993~. One important point made by the authors is that dopants can occupy either hexagonal or cubic sites in the more complex SiC polytypes. These different environments give rise to different binding energies and care must be taken when deconvolving the separate contributions from Hall data. Pensl and Choyke showed that the relative abundance of the various nitrogen dopant levels corresponded to the ratio of available binding sites. For 4H-SiC, the hexagonal (h) and cubic (k) binding energies were measured to be 45 meV and 100 meV, respectively. A level ratio of 2:1 was found in 6H-SiC, reflecting the fact that two-thirds of the sites have cubic bonding. In 6H-SiC Hall measurements, the measured ionization energy of the hexagonal site was 85.5 meV, while the cubic sites were 125 med. The experimental resolution was insufficient to resolve the two separate cubic donor energy levels. In 3C-SiC, a value of 48 meV was determined. Typical compensation values were one to two orders of magnitude below the observed electron concentration. Similar measurements for aluminum-doped SiC yielded an acceptor ionization energy of roughly 200 meV for each of the three most common SiC polytypes. These values are all smaller than those measured optically due to a reduction in the average electron energy when donor spacing is small. In commercial SiC technology, ion implantation plays a major role. Due to the excellent stability of SiC, the material lends itself well to high-temperature annealing for implantation-related damage removal. Marsh and Dunlap

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Materials for High-Temperature Semiconductor Devices TABLE 4-3 Additional Ohmic Contact for SiC Contact Resistivity Metal Post-Treatment (Q cm2) Description Reference Nickel High temperature Ohmic to McGarrity et al., source/drain limited 1992 to 300 C or less Aluminum High-temperature Gate McGarrity et al., anneal 1992 Gold, platinum, titanium, > 450 C 10-3 to 104 hafnium, cobalt to n/p type SiC Morkoc et al., 1994 To heavily doped 10 p-type WSi2 4 x 104 Delaminates at Morkoc et al., 1994 600 C Au/Ta/SiC 900 C in air 1 x 10-5 Morkoc et al., 1994 (1970) characterized the first ion-implanted SiC junctions in 1970 that were formed by implanting e-type dopant into a p-type substrate at room temperature. More-modern approaches utilize a process in which the target material is heated during the implantation (Ghezzo et al., 1992~. Ghezzo et al. (1993), at GE, have demonstrated improved diode characteristics using boron-implanted 6H-SiC at high temperature with a post-annealing. A summary of the needs for ion implantation for SiC devices has been presented by D.M. Brown et al. (19941. Doping of GaN A review of the doping of GaN is given by Morkoc et al. (19941. Unintended doping of GaN, as well as A1N, results from an e-type background concentration. With improved crystal growth techniques, background concentrations for GaN have recently been reduced to as low as 10~6 cm~3. For example, Nakamura et al. (1992) have reported GaN bulk mobility, ~ = 600 to 1,500 cm2/V s at 300 and 77 K, respectively, in an undoped sample with n = 4 x 10~6 cm~3. Nitrogen vacancies are considered to be the most likely candidate as a donor site. Control of the nitrogen overpressure appears to be critical to influencing this type of defect. A resurgence in activity has occurred with the recent 42 observations by Amano et al. (1989) of low-energy electron-beam activation of magnesium-doped GaN to produce p-type GaN. Nakamura et al. (1992) have improved on these results by using low-energy electron- beam irradiation during the implantation. They also discovered that annealing the magnesium-doped GaN at 700 C in nitrogen produced equally good p-type GaN. The process was reversible with NH3 anneal where hydrogen is found to be a compensating agent. Molecular- beam epitaxy (MBE) processing that is free of hydrogen has been found to induce p-type conducting in the as- grown state. Numerous other dopants have been used in an attempt to produce p-type GaN, with zinc as the most effective p-type impurity. A list of these are presented in a review article by Morkoc et al. (1994~. In addition, isolation regions have been produced by proton ion implantation. Energies and doses were unspecified except to say that the energies and doses were selected to produce uniform compensation across a 1-,um- thick film of 1 x 10~7 cm~3 e-type GaN epitaxial layer. Doping of A1N There has been little work in the area of doping of A1N. A persistent contaminant of A1N is oxygen. It is clear that major improvements and much more work is A ~A ~ ~. r ~

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Generic Technical Issues Associated with Materials for High-Temperature Semiconductors TABLE 44 Ohmic Contacts for GaN Contact Resistivity Metal Post-Treatment (Q cm2) Description Reference Titanium 25 A/ 250 C for 30 s 7.8 x 10 ~Ohmic to source Khan et al., o Gold 1,500 A & drain MESFET 1993a, b Silver Schottky Gate metal Khan et al., No other info. 1993a, b Ti/Al/n-GaN 900C for 30 s 8 x 10 ~Good ohmic Lin et al., 1994 Gold and Contact resistance not reported, Nakamura et Au/Ni/p&n-GaN but reasonable contact resistance al., 1991 deduced from operating voltage of 4 V at 20 mA Al/n-GaN 10 ~Forest and Moustakas, 1993 Au/GaN 10-3 required to produce useful device-quality materials. Ion- implantation doping of A1N is virtually unknown, and work in this area will require quality substrate materials that are only recently becoming available. Doping of Diamond Boron is the only universally recognized acceptor impurity that can be controllably introduced into diamond. Until recently, only a small portion of the boron in diamond was electrically activated. It can now be introduced and nearly 100 percent electrically activated by a series of implantation processes to concentrations of 1 ~ 10~9 cm~3. The same investigator stated that he has activated phosphorous in diamond at 80 MeV by a similar procedure (Prinz, 1994~. GATE OXIDES AND INSULATORS This section examines issues related to the growth of suitable gate oxides and insulating layers for field effect devices. These are either thermally grown oxides, where appropriate, or epitaxially grown higher bandgap layers, where stable, high-quality oxides are difficult to achieve. Not included in this discussion are films that are deposited 43 to provide electrical isolation (e.g., silicon oxides or nitrides). Although there may be fundamental problems with the identification of materials that will withstand the high-temperature environment for which the associated devices are intended, the committee regards these issues as secondary in the sense that they are not intrinsically related to a particular material choice. Gate Oxides and Insulators for SiC SiC benefits from its amenability to thermal oxidation to form the well-understood, characterized, and utilized SiO2. The general consensus is that the oxidation of SiC follows that of the well-established silicon oxidation process. The total oxide thickness, c, can be estimated by: c2+Ac=B(t+to), where t is the duration of the oxidation process, A and B are temperature-dependent rate constants, and to is a constant that depends on the initial state of the surface (Deal and Grove, 1965~. As for silicon, oxidation rates and oxide quality will vary according to the SiC polytype, the crystal orientation, defect density, doping level, and the nature of the oxidation conditions (i.e., whether carried out under wet or dry ambient conditions). For

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Materials for High-Temperature Semiconductor Devices example, Laukhe et al. (1981) found that the 3C, 4H, 6H, and 15R polytypes oxidized at different rates on the silicon face, with 3C oxidizing approximately 20 percent more rapidly than 6H. The oxidation of the 6H and 3C polytypes on the silicon and carbon faces has been characterized, contrasting the differences brought about by either wet or dry oxidation and determining values for the rate constants A and B in the above equation (Powell et al., 1991; Petit et al., 19921. Significant differences in the oxide growth rates of polytypes on the carbon face, as well as the silicon face, were found. The differential oxidation rates were used to provide a map of the polytype distribution for the silicon and carbon faces of SiC films. Little difference in oxidation rates of the polytypes were found when the silicon face was oxidized in a wet ambient or when the carbon face was oxidized in a dry ambient; conversely, the 3C polytype oxidizes more rapidly in dry oxidation of the silicon face and the 6H more rapidly in wet oxidation of the carbon face. These differences are obviously of critical importance in the fabrication of MOS-quality devices. However extensively characterized, the quality of the SiC/oxide interface will still require considerable improvement before a reliable device technology can be assured. For example, in Singh and Rys' (1993) comparison of wet and dry oxidation of e-type, silicon-face 6H-SiC, capacitance-voltage measurements revealed the necessity for a post-oxidation in argon. Otherwise, the capacitance-voltage curves showed no accumulation after the first trace was taken. Under dark conditions, inversion did not occur-perhaps because of the lack of minority carriers due to the large bandgap of the SiC. Other work has found that sweeping from accumulation to inversion in real time required heating the substrate to 860 C (Morkoc et al., 1994~. The extensive characterization of oxide samples revealed interface trap states between mid-10 cm~~ evil and 10~2 cm~~ eve, with lower trap densities for dry compared with wet oxidation, but comparable emission time constants (a ps). The nature of the traps may differ depending on whether the oxidation Is wet or dry, however, these values of interface states density has found corroboration in other work on n- and p-type samples (Morkoc et al., 1994~. Finally, a good dielectric strength of 6 x 106 V/cm has been measured for thermally grown oxide on 3C-SiC (Fung and Kopanski, 1984~. Future approaches to form a device-quality oxide may involve the use of alternative oxidation sources, such as N2O. 44 Gate Oxides and Insulators for the Nitrides Based on the wealth of experience and research on compound semiconductors such as GaAs and InP, it is not expected that a suitable oxide-based device technology will be developed in these materials. However, the GaN/AlN system may have particular advantages in formation of metal insulator semiconductor (MIS) and electrically insulating structures capitalizing on the reasonable lattice-match of the A1N and GaN (2.4 percent), and the differences in bandgap (6.2 eV for A1N, 3.4 eV for GaN). The higher bandgap A1N or AlxGa~ xN can then serve as an insulator, playing the same role as AlxGa~ xAs in GaAs/AlGaAs sem~conductor-insulator- sem~conductor field effect transistors (SISFETs), and the device structure would closely approximate that shown in Figure 4-1. To give furler impetus to this approach, previous measurements have indicated that the resistivity of unintentionally doped AlxGa~ xN increases rapidly with increasing aluminum mole fraction, becoming insulating at about x = .20 (Figure 4-2), minimizing the possibility n 1 . r 1 1 I I ~ ~ ~ ' ' Film , Ll . ~1 Am Source _~_ 50,um Drain AlGaN n- GaN AIN Sapphire FIGURE 4-1 Schematic of the device structure for a AlN/AlxGal xN SISFET. SOURCE: Morkoc et al. (1994).

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Generic Technical Issues Associated with Materials for High-Temperature Semiconductors 1o6 104 E 1 0 o - ._ en 1 0 ._ in a) lo: 10-2 10-4 - . 1 ~ . ~ 1 1 1 1 1 1 1 0 0.1 0.2 0.3 0.4 Composition, x 1032 I I HE 2~ ~3 ._ 1 0 I _ 1021 co - 1 o20 ~ _ _ 1019 = 0 ._ 18 17 ~ o a, . ~ ct FIGURE 4-2 Increase in resistive of unintentionally doped AlxGa, xN win increasing aluminum mole fraction. SOURCE: Morkoc et al. (1994). of leakage through the A1N insulator layer. Critical to the feasibility of the approach will be the nature of the interface between GaN and A1N (or GaAlN), as well as the quality of the insulator material itself. Optimism for a high-quality interface is built upon the already demonstrated high-quality operation of an AlGaN/GaN modulation-doped field effect transistor (Khan et al., 1993a). Modulation of the GaN/AlN interface can be inferred from the ability to modulate the two-dimensional electron gas and achieve complete pinch-off of this transistor. Gate Oxides and Insulators for Diamond No material-compatible oxide or insulating layer has been identified for the diamond-based technology thus far. Device realizations have generally comprised MESFET- like structures. The production of MOSFETs using CVD oxides has also been attempted. ETCHING Pattern transfer by etching is a critical component of any device and circuit fabrication scheme. For certain 45 stages in the fabrication sequence, such as etch cleaning of the substrate surface, or etch delineation of patterns having large dimensions (tens of microns), wet chemical etching is the preferred process. Many of the materials under discussion here, such as SiC or diamond, are relatively inert to general chemical etchants. However, constraints of high-resolution features, control over etched profiles, and etch-rate and process reproducibility have generally led to dry etching techniques as the choice for manufacturing-compatible processes. In this regard, dry- etch chemistries and processes have already been applied and are meeting with reasonable success. The manufacturing-related issues of uniformity and control will have to be further explored, as is being done even for the silicon-based technologies. Furthermore, although the initial applications of dry etching to the wide bandgap materials have met with success, much more work remains in order to delineate the basic mechanisms, the rate-limiting steps, the quality of the etch surface, the possibility of etch-induced damage, etc. Etching of SiC Successful reactive-ion etching (RIE) has been carried out on SiC, primarily incorporating the same chemistries that have been established and proven successful for silicon-based technology (i.e., the use of fluorine- containing gases that reacts with silicon to form the volatile SF41. Pan and Steckl (1990) have utilized SF6, CF3Br, and CHF3 mixtures with oxygen and generally achieved modest etch rates of a few hundred angstroms per minute. A factor that differs from conditions in which most silicon RIE is carried out is the generally large component of oxygen utilized (35-90 percent by flow), thought to be important in removal of the carbon through generation of the volatile product, CO2. Chlorine (Balooch and Olander, 1992) and chlorine-containing gases, such as CC14 (Lo and Huang, 1992), have also been utilized, as well as CF4/O2 (Padiyath et al., 1991) and NF3/O2 (Brown, 19931. Although the etch rates obtained range from 50-200 nm/min and are comparable to those found for RIE of silicon under a very fluorine-rich etch condition (SF6 + 35% 02; Pan and Steckl, 1990), silicon was found to etch about an order of magnitude more rapidly than SiC. Generally, the strong bonding of SiC makes it a difficult material to etch by wet chemical means at

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Materials for High-Temperature Semiconductor Devices reasonably low temperatures. However, Shor et al. (1994) have found that etching using laser illumination of a sample immersed in an HF-based solution has produced were reported by Efremow et al. (1985), using ion-beam- assisted etching that utilized 2 keV Xe+ ions with a flux density of 1 mA/cm2 in the presence of NO2 reactive gas. etch rates well in excess of 1 ,um/min. Such a Although the average pressure of the chamber was photoelectrochemical etching technique may have 2 x 104 Torr, the equivalent reactive flux of NOR on the applicability to certain fabrication requirements, such as deep etches that may be needed for sensor fabrication. Etching of the Nitrides: GaN and AIN Dry etching of the nitrides has benefited from the previous extensive research on gallium and aluminum- containing semiconductors, in a manner similar to SiC and silicon. With respect to the periodic table of elements, the successes demonstrated thus far indicate that it is the Column III elements that provide the major constraint to the RIE of the nitrides. Generally, chlorine-based chemistries have been applied to the etching of GaN and A1N, comprising gases such as CCl2F2, BC13 (Pearson et al., 1993; Lin, 1994), SiCl4 (Adesida et al., 1993), and SiCl2F2 (Morkoc et al., 1994~. Adesida and colleagues achieved a GaN etch rate of 600 A/min using SiCl4 but only at higher voltages, suggesting a rather low chemical enhancement in this process. Similarly, Pearton et al. utilized electron cyclotron resonance radio frequency etching of the nitrides in CC12F2 and BC13, at relative low bias ~ ~ 200 V), low pressure, and low microwave power. The etch rates were approximately 200 A/min, which is modest even at these low pressure and bias conditions. However, Lin et al. (1994) used the BC13 chemistry and were able to obtain greater than 1,000 A/min etch rate. Temperature-dependent etch-rate studies would help to more clearly reveal the rate-limiting steps in current dry- etching approaches and would also give a better idea of the ultimate etch rates and profiles achievable. In a manner similar to forming selective GaAs to AlGaAs etch processes, the addition of excess fluorine to a gas composition will provide high selectivity of etching GaN with respect to A1N (Pearson et al., 19931. The etch anisotropies obtained for all methods used have been excellent. Etching of Diamond Diamond is commonly regarded as an inert material that cannot be etched by boiling acids or bases. Nevertheless, diamond etch rates as high as 200 nm/min 46 diamond corresponded to 10-5 Torr, presumably responsible for the impressive etch rates that were achieved, with etch-rate selectivities to aluminum masks at a ratio of 20:1. Other methods that have been used to etch diamond are (1) the use of kinetic energy beams of oxygen or oxygen-containing molecules or radicals and (2) electrolytic etching. Electrolytic etching is generally limited to removal of defect-ridden or otherwise conducting regions of diamond, however. DEFECT ENGINEERING AND CONTROL Every materials system presents new challenges in defect engineering to produce and maintain desired performance. High-temperature materials are robust at 300 C, but may be vulnerable at the high process- temperatures required. This section evaluates crystal perfection, processing, and electrical performance for diamond, SiC, and GaN. The purpose is to identify fundamental limitations and focus areas for precompetitive research and development leading to commercialization. Semiconductor materials composed of low atomic number elements possess strong covalent bonds. As a result they exhibit large energy gaps, high elastic moduli, high phonon frequencies, high thermal conductivity, and high melting points. These properties, which can be exploited for high-temperature electronics, have consequences in processing and perfection. The formation energy of simple point defects (vacancies and interstitials), Ef(V), Ef(I), can be estimated to first order as the heat of vaporization, AH. This energy represents creation of a bulk defect from a surface source, and it is typically valued at twice the bond energy. Thus, a lower bound for Ef is twice the energy gap, Eg. With Eg = 3 eV, Ef is expected to be very large. These large values preclude doping by diffusion and present a bottleneck for defect control (e.g., during oxidation and contact formation). If process temperatures do not exceed one-half the melting temperature, stoichiometry (the equivalency of conjugate defects on each sublattice of a compound) can be maintained,

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Generic Technical Issues Associated with Materials for High-Temperature Semiconductors dislocation motion is limited, and the incorporation of unwanted contamination is reduced. However, Larkin et al. (1993) have shown that dopant incorporation is dependent on the silicon/carbon ratio in nonequilibrium growth. If electrical properties scale with the energy gap, most nondopant impurities should have deep energy positions, with energy of the trap level ET > 1 eV, and therefore they should not contribute to leakage current generation in junctions at 300 C. Large concentrations of these trap states, however, could result in semi-insulating behavior. The compensation level (i.e., the difference between the number of acceptors and the number of donors, NA ~ ND) must be defined in device-quality material, and a theory and catalog of defect and impurity energy positions must be established. Since directional covalency dominates bonding, local relaxation from fourfold coordination can greatly reduce defect and impurity incorporation energies. For instance, the nitrogen donor in diamond lowers its symmetry from a substitutional site to produce a deeper state than predicted by simple theory. Davies (1994) has recently reviewed the properties of defects and impurities in diamond. Nitrogen in 6H-SiC shows persistent photoconductivity indicative of this relaxation. The difficulty in p-type doping of these wide bandgap materials may similarly be related to the preference of Group III atoms for threefold coordination. In general, low atomic number elements from groups III, IV, and V act as electronically passive terminations for surfaces and defects. Phosphorus-containing compounds exhibit less sensitivity of device performance to defects and more passive surfaces. The intrinsic carrier mobility and minority carrier lifetime in these materials must be characterized and understood. In the mid-1950s, these properties were well-defined for silicon, providing a benchmark for material quality. This foundation does not yet exist for high-temperature semiconductor materials. SiC, the most developed material of the group, has a reported minority carrier lifetime of 10-9 s, and carrier mobilities that increase with activated behavior above room temperature. But the issue arises whether these properties are intrinsic or reflections of high defect densities that are not yet characterized. Swedish researchers have reported minority , ~ carrier lifetimes in 6H-SiC of 0.45 As (Kordina et al., substrates such as sapphire. The electrical properties of 1995~. these dislocations have yet to be understood. They are of Passivation of surface conduction and recombination is essential to device function. It is essential to measure interface properties at the temperature of operation. Kang et al. (1993) have shown that quasi-static C-V measurements at 20 C can underestimate by an order of magnitude the density of interface states of 6H-SiC/SiO2 that are active at 240 C. Performance at 400 C cannot be predicted. The porosity, state of stress, and oxidation mechanism of SiC must be understood. Other issues also remain: (1) there is a factor of 10 higher oxidation rate on (111) carbon-terminated versus silicon-terminated surfaces that has not yet been explained, (2) the true density of interface states is unknown, and (3) the failure mechanism for gate-oxide breakdown at operational temperatures is not known. The quality of critical insulators (e.g., gate oxides in MOSFET technologies), and hetero-interfaces (e.g., oxide-to-SiC or GaN-to-AlN) will be important determinants of not only device performance but also device reliability. Defects in the oxide layer and at the oxide-semiconductor interface may arise through propagation of defects from the semiconductor substrate, may be correlated with the manner of oxidation (e.g., whether carried out in a wet or dry ambient and at a particular temperature), or may be introduced by subsequent processing (e.g., gate recess etching performed by reactive-ion etching). As current silicon technology has shown, these problems are aggravated as the oxide layers have been made thinner in order to appropriately scale device dimensions down to achieve denser, faster circuits with higher functionality. The reliability of heterojunction devices such as SISFETS will similarly depend on the nature of the interface; interface roughness and interface state densities will affect device mobilities and increase device noise, as well as long-term performance. YIELD 47 High yield in device and circuit manufacturing requires high-quality substrates and wide process margins. Typical SiC contains 20-100 micropipe voids and 104 to 105 c~2 dislocations. GaN is grown epitaxially with anoroximatelv 10l cm-2 dislocations on high misfit

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Materials for High-Temperature Semiconductor Devices no apparent consequence in GaN blue light-emitting diodes, but these dislocations may limit yield for other materials or applications by providing fast diffusion paths for unwanted impurities during processing or by acting as junction shorts. Micropipes act as premature breakdown sites in SiC junctions (Fazi et al., 1993~. Material screening should evaluate the role of microplasma sites in premature breakdown at operational temperatures. Dopant uniformity is essential to process control. Implant activation for aluminum and boron in SiC requires further development (aluminum exhibits < 1 percent activation). Activation is dependent on the perfection of the host material. Nonuniformity across a wafer suggests that spatial mapping of defect densities (X-ray topography, research. photoluminescence, etc.,) could provide a valuable characterization matrix in materials development. Of course, control of dopant compensation in the 10~4 cm~3 range is a necessity. The role of transport anisotropy must be evaluated in the development of a planar integrated circuit technology. The mobilities and effective masses are very anisotropic for 6H- and 15R-SiC. By contrast, 4H-SiC is more isotropic. Etch and metallization processes can create defects and yield limits. The absence of a complete wet-etch technology for high-temperature semiconductor materials means that RIE is the default process. Defect introduction and stability for each RIE application must be evaluated. Contact formation and interracial reactors can modify band-edge offsets and, hence, contact resistance and heterojunction device performance. These reactions and process response surfaces must be understood. Alternative approaches, such as layer bonding and buffer-layer engineering, should be pursued. The small lattice constants of the high-temperature semiconductors have no available match among the mature substrate materials technologies. In summary, process yield is dependent on the critical defect density and the chip area. The next phase of research and development on high-temperature semiconductors must identify the critical defects and improve materials and processes to reduce their density to economically tolerable levels. 48 DEVICE RELIABILITY The expected applications for high-temperature electronics (e.g., aircraft, automotive, and power systems) require high reliability. However, the temperatures of operation are typical of accelerated aging conditions for current systems. The purpose of this section is to identify potential failure mechanisms and suggest areas of research for remediation. The current design approach is to extrapolate low-temperature concepts to higher temperatures. However, new failure modes may exist in this unexplored region with new materials systems. Detection of these new modes is a critical subject of n~gn-temperature systems will cycle between room temperature and higher operation temperatures. The mechanical design of these components must include differential thermal expansion and consequent fatigue tolerance as factors in materials selection. Current solder alloys will melt by 300 C. New alloys with both mechanical strength and systems compatibility must be found. Polymer dielectrics for encapsulation and printed circuit boards must similarly be redesigned. Integral ceramic packages are a favored replacement. Electromigration of interconnect lines is thermally activated, as well as current density dependent. For silicon-on-insulator (SOI) applications, aluminum (TM = 600 C) must be replaced. Tungsten and copper are likely candidates. Thermal management is particularly critical for high- power applications at high temperatures. Silicon bipolar devices exhibit "thermal runaway" at 200 C due to free carrier generation. SOI limits rise to 350 C due to the smaller volumes of silicon. Gate oxide and hot carrier degradation are cumulative effects. Their temperature dependence is controversial. The role of temperature in aging and operation must be understood. Contact degradation is a serious problem for III-V materials at high temperature. Pt-GaAs impact avalanche transit-time (IMPATT) diodes degrade as the platinum metallization reacts to form PtAs2 and PtGa. Also, defect migration from the contact can compensate the doping level and change the device avalanche voltage. Diffusion barrier layers and stable heterogeneous systems must be designed.

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Generic Technical Issues Associated with Materials for High-Temperature Semiconductors In laser devices, high injected current densities lead to degradation by "dark-line-defect" formation (electronically stimulated dislocation motion). The high elastic moduli of diamond, GaN, and SiC inhibit dislocation motion. In addition, the low atomic number elements tend to create electronically passive defects and interfaces. Dislocations appear to be electrically benign in 49 GaN. These materials should display better operational reliability than GaAs, InP, and ZnSe. In summary, the strategy for reliability assurance is (1) re-evaluation of known failure mechanisms in a high- temperature applications context and (2) identification and remediation of new failure modes in these new materials systems and environments.

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