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5 High-Temperature Electronic Packaging Preceding chapters of this report have presented the status and potential of the use of various semiconductor devices for high-temperature applications. Depending on the given application, the operating temperature of these devices varies from 150 °C (automotive electronics) to 1000 °C (a high-temperature interconnect for a thermionic integrated circuit; Fendrock and Hong, 1990~. Adequate packaging has to be provided to build functional modules based on these devices, however. The primary issues to be considered in high-temperature electronic packaging are: (1) characterizing materials and their interactions at high temperatures, (2) minimizing mechanical stresses caused by thermal expansion mismatches, (3) providing a suitable path for heat dissipation, and (4) providing environmental protection. The first two items are of particular importance as the upper temperature limits of operation are increased. The overall goal of packaging is to ensure reliable operation of semiconductor devices. The selection of the packaging method used is based on cost/performance tradeoff decisions, complexity of the devices involved, system requirements, and the operating temperature range. There are many different packaging and interconnection schemes that can be successfully applied to overcome the shortcomings of conventional packages for high-temperature operation. A successful package design will satisfy all given applications and system requirements. For example, microwave packaging will have to meet additional requirements such as impedance matching, low dielectric loss at microwave frequencies, low sensitivity of dielectric and conductors to temperature changes, and low capacitance of interconnect to the backside of radio frequency ground plane. One approach to providing hermetic electronic packaging suitable for operation at higher temperatures is to rely on existing packaging technology such as either the use of single metal packages 51 with electrical feedthroughs isolated by glass beads or the use of multilayer ceramic packages (single or multichip). Both types of packages have been successfully used for high-temperature electronics. Another approach is to seek improved packaging materials and designs that better match the needs of high-temperature electronic systems. This chapter focuses on the off-the-shelf packaging technologies used in both the first level of high- temperature electronic-system packaging, usually defined as the chip packaging, and the second-level packaging, which is defined as package-to-board interconnections. Since some large hybrid microcircuits and multichip modules closely resemble both first- and second-level packaging and because the high-temperature electronic boards are often ceramic with thick- or thin-film metallization, they share the same materials and assembly processes and are considered here to be the same high- temperature electronic-packaging technology (Palmer and Heckman, 1978; Palmer, in press). CHIP PACKAGING High-temperature electronic-packaging technologies have been developed at least five times over the last four decades (Palmer, in press): vacuum-tube computers (late 1940s), initial encounters with high-velocity missiles and space probes (1950s), nuclear power plant instrumentation (1960s; Kueser, 1965-1966), oil/gas/geothermal well- logging instrumentation (late 1970s; Sinclair, 1979; Veneruso, 1979), and special solar and Venus surface probes (early 1980s; Jurgens, 19821. Current applications include volume-limited power supplies and conversion units, industrial process tracers, and automobile engine controls. Since these applications are of limited volume, the packaging of these devices is usually expensive due to
Materials for High-Temperature Semiconductor Devices the lack of effort for further development and optimization at the package level. The high-reliability packaging schemes used today for long-service military systems do offer considerable high-temperature-operation capability (Palmer, in press). The most widely used metal package is gold-plated Kovar (an alloy of 53 percent iron, 29 percent nickel, and 18 percent cobalt). The finish is usually a high-temperature-res~stant 24-karat gold that Is plated to a thickness of 100 micro-inches or greater. The underplating should be an electroless nickel plating containing 8-12 percent phosphorus that is plated to a thickness of 100-200 micro-inches (Licari and Enlow, 19881. The output leads are sealed into the Kovar package sidewalls or floor using glass-to-metal seals or ceramic feedthroughs. Metal packages consist of two configurations: plug-in or flatpack types. These metal packages can be designed with welded lids, thus assuring seal integrity at high temperatures (Palmer, in press). These packages have been evaluated to 400 °C with satisfactory results. The most common failure is due to the lack of mechanical and electrical integrity of the glass or ceramic feedthrough at high operating temperatures and after thermal cycling (Johnson, in press). As the service temperatures are increased, the electrical resistance and the hermeticity of the seal is degraded. Since the glass seal is formed at 500 °C, other types of seals need to be investigated for operating temperatures above 400 °C (Johnson, in press). Another widely used type of package that also provides good high-temperature performance along with hermeticity is the ceramic package. The most attractive ceramic package for use in high-temperature applications is the aluminum-nitride package; however, the most often used is the less costly alumina. Ceramic packages are manufactured using a cofired tape process and have an advantage over metal packages because they can avoid the use of expensive fragile glass-to-metal seals. Ceramic packages can be designed as integral-lead packages, leadless chip carriers, and leaded chip carriers. An advantage of the integral-lead package is that the input/output leads can be spaced very closely. The packages may be sealed either by soldering or by welding. Temperature limitations for ceramic packages depend on the type of sealing method used. These packages are not suitable for high-current applications due to the res~st~vity of the refractory metals used as conductors. The use of 52 packages with short tungsten conductors is also recommended since these packages will increase in resistance by about five times from room temperature to 500 °C. In addition, the insulation resistance at elevated temperature decreases by approximately 40 percent (Figure 5-1; Johnson, in press). Today's plastic packages are not suitable for applications above 150 °C (Palmer, in press). For example, the glass transition temperature of commonly used packaging epoxies lies in the range of 130-170 °C, which limits the operating temperature range of the package. Unlike their hermetic counterpart, plastic packages subject wire bonds to extreme stresses if the package undergoes large temperature swings (e.g., -55- 300 °C; Harman, in press). Silicone-gel coatings have recently been evaluated as an alternative to hermetic packages for high-reliability applications and the results have been promising. The continued use of plastic packages is highly desirable, thus the development of new higher-temperature materials is of great importance. Besides the selection of the type of package, it is necessary to select the substrate, the component attachment method, the chip interconnection technique, and the sealing process. Understanding both material 1014 lo13 ends 10~, u) o .~ .2 .cn U' 1o1o _ 109 _ 1o8 _ 1o7 _ 1o6 _ - Forsterite \ \\\\ \99% Alumina . Alumina \~\ `~` " \ Magnesia Steatite '- _ Sapphire jo5~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ I 200 400 600800 1000 1200 Temperature (°C) FIGURE 5-1 Decrease in insulation resistance as a function of temperature. SOURCE: Johnson (in press), ~ IEEE.
High-Temperature Electronic Packaging behavior and material interactions is of great importance. As the conventional materials are used beyond the temperature range for which they were originally developed, new failure mechanisms appear. The result is that some material systems are no longer viable. Even when the available materials are individually suitable for use at high temperatures, the devices may fail due to thermomechanical stresses or other interactions between various components of the material system. In the following section, brief descriptions of standard attachment and assembly processes are Riven. Sunnortina information on materials properties IS also supplied. J - ~ r ~of -rr--~--~o . . . SUBSTRATES The selection of the substrate material is dictated by the combination of thermal, electrical, and mechanical design requirements for the given application. Key substrate properties for materials presently being used are given in Table 5-1. Alumina, Al2O3, is the most widely used ceramic substrate, and many high-temperature electronic systems have used this material without difficulty (Herman, in press). Both alumina and AlN can be used as a substrate in two different ways: they can provide the mechanical support structure for the deposition of thin-film interconnections or they can house part of the interconnection structure (cofired with molybdenum or tungsten). A significant advantage associated with the use of AlN and SiC is their high thermal conductivity and coefficient of thermal expansion, which is close to that of silicon (and almost all wide bandgap semiconductors). Diamond can also be used as a substrate material. When using such a substrate material, less stress between the substrate and chip is generated during the temperature excursions encountered in the manufacture and operation of the substrate assembly. It should be noted that SiC has a high dielectric constant and high dissipation factor limiting its use as a substrate. The limitation of the use of AlN is the availability of chemically compatible thick-film pastes. Recently, a broad range of thick-film-paste materials for use on and in AlN substrates, including gold-based conductors. multilaver dielectric, and resistors have been developed (Tables 5-2 to 5-4; Chitale et al., 1994; Shaikh, 1994~. Diamond is a promising material to serve as a substrate for high-temperature electronics. It has the 53 highest thermal conductivity of any material at room temperature (1,700 W/m K). Diamond use is currently restricted by its cost and limited compatibility with thin- and thick-film metallization. However, the extremely high thermal conductivity of diamond, coupled with its electrically insulating nature and very low thermal expansion, make it a worthwhile subject for studying the manufacturing technology issues that must be resolved in order to make available 1-mm-thick diamond material in 100 mm (4 in.) or larger sizes at reasonable cost (Eden, 19941. THICK-FILM AND THIN-lILM METALLIZATION The desired characteristics of a metallization system are good adhesion to the substrate, low stress, good electrical conductivity, and minimal reactions at subsequent processing or assembly steps. Thick-film conductors based on noble metals have been successfully used for high-temperature applications (Bonn and Palmer, 1980: Shaikh, 19941. Typical metallurgies include tungsten, molybdenum, gold, Pt/Au, Pt/Ag, Pd/Ag, and Pt/Pd/Ag. The properties of most common metals that are considered for multilayer, cofired ceramic substrates are given in Table 5-5 (Palmer, in press). Electrical properties of thick- or thin-film conductors differ at high temperatures. The resistivity always increases and the temperature coefficient of resistivity always changes. For example, the temperature coefficient of resistivity of thin-film gold is +0.0016/°C; for platinum it is +0.0027/°C and for tungsten it is 0.0046/°C. These resistivity changes must be taken into account for high-temperature applications. The disparity in thermal expansivities between the dielectric material (either substrate or interlevel dielectric) is about 3.7-6.8 ppm/°C, and such metals as silver (19 ppm/°C), gold (14 ppm/°C), and Ag/Pd (~ 19 ppm/°C) is substantial. This difference causes the metal to shrink more than the ceramic during processing and assembly or during power cycling. The cylindrical metal in the via hole begins to shrink more than the surrounding ceramic and can cause an annular void space between the via metallization and the ceramic. The most promising materials for high- temperature applications, from a mechanical point of view, are A1N substrates with cofired tungsten
Materials for High-Temperature Semiconductor Devices TABLE 5-1 Properties of Ceranuc AIN, Ceranuc SiC, Glass :E Ceramics as Compared wide 90 percent Alumina Substrate Properties Ceramic A1N Ceramic SiC BeO Glass + Ceramics 90% A12O3 20 Thermal conductivity (W/m K) 230 270 260 5 Coefficient of thermal 43 37 75 30-42 67 expansion (25-400 C) (10- / C) Dielectric constant at 1 MHz 8.9 Flexural strength (Kg/cm2) 3,500-4,000 42 6.7 3.9-7.8 9.4 4,500 2,500 1,500 3,000 Thin-film metals Ti/Pd/Au Ti/Cu Cr/Cu.Au Cr/Cu NiCr/Pd/Au Thick-film metals Ag-Pd Au Au.Cu.Ag-Pd Cu Ag-Pd Cu.Au Cofired metals W Mo W Au.Cu.Ag-Pd W.Mo Cooling capability Air (°C/W) 6 5 5 60 30 Water (°C/W)a ~ 1 < 1 ~ 1 < 1 < 1 a External cooling. conductors. Nickel is plated on the exposed conductors and is diffusion-bonded to the base metal for enhanced a&esion. Following the nickel diffusion process, a layer of gold is deposited to prevent formation of nickel oxide and to enhance Nettability during subsequent soldering or brazing processes. The final plating step is the application of heavy gold on the wiring pads to accommodate chip interconnection bonding. The a&esion between A1N and tungsten is mechanical in nature, where joining strength is presumably provided by grain interlocking or anchoring across the interface. The microstructurally toughened interracial a&esion also assures that the cofired multilayer substrate maintains the high thermal conductivity and mechanical strength of typical monolithic A1N (Chiao et al., 1991~. Thin-film metallizations have also been successfully used at high temperatures. The metallurgies most often used are a gold base with titanium or chromium for obtaining adequate a&esion and platinum or palladium as barrier layers. Gold is a suitable metal for this application because it has superior conductivity, protects the surface from environmental attack, and helps ensure bondability. 54 For diamond substrates, various thin-film conductors have been reported. For example, Au/Pt/Ti metallization was studied by Davis (19931. In this system, platinum prevents interdiffusion between titanium and gold up to temperatures of 400 °C during the annealing process. However, when annealed at 500 °C, decorated patterns are observed on the surface of the gold layer, indicating interdiffusion between the deposited metals. After annealing at 400 °C, the sheet-resistance value had increased by 40 percent. Furthermore, at 500 °C a 139 percent change in the value of sheet resistance was observed. Other examples of suitable metallurgical systems are Au/Ti-W and Au/Cr. Au/Ti-W exhibits good a&esion at temperatures up to 300 °C, but at 450 °C the a&esion degradation can be attributed to surface changes that resulted from the diffusion of Ti-W into the gold. Au/Cr appears to be more stable than Au/Ti-W, and improvements in a&esion have been observed after a 450 °C anneal. Unless they are suitably protected, many thin films experience increases in resistance when heated in air due to their oxidation. Ultimately, they may be converted to insulating films. It has been found that the increase in
High-Temperature Electronic Packaging TABLE 5-2 Metall~zations for A1N Substrates 5835 D-8813 8835-1A Product Number D-8835-1D D-9633-Da 9601-N D-9913 Metal type Pt/Au Gold, Gold Ag/Pd Ag/Pd Ag/Pd Silver alloyed Fired Sickness, ,um 12-15 8-10 8-13 7-10 9-12 12-15 9-13 Resistive, mQ/O <60 <4 <7 <4 <35 <3 <2 Adhesions, initial Kg Adhesion, 200 hrs at 150 °C, Kg 4.5 > 5.0 >2.5 >2.5 >6.0 >3.0 Thermosoruc 25,um > 14 > 12 > 14 > 6 > 6 gold wire, g Ultrasonic 250 Em . . aluminum wire, g > 400 > 250 > 350 > 250 >5.0 >5.0 >3.0 >3.0 a This Ag/Pd conductor }has He highest initial adhesion. Unfortunately it Is incompatible win all over ES~ick-f~lm materials for A1N. b Adhesion, 90° pull, 2 nun x 2 non pads. resistance of a film is considerably greater than can be accounted for on the basis of only reduced thickness of the conductive portion of the film resulting from oxidation of the surface. This is due to the fact that oxidation occurs along the grain boundaries of the film as a result of either oxygen diffusing in from the surface or from oxygen trapped internally that precipitates at the grain boundaries and forms an insulating phase. COMPONENT ATTACHMENT The primary method of securing the device to the substrate (die attach) is by diffusional reaction of the backside (usually metallized) with a substrate gold metallization. This joint is designed to elastically absorb the thermomechanical stress that accumulates between the chip and the ceramic substrate, conferring excellent fatigue resistance. There are three types of die-attach materials that are most suitable for application in high- temperature electronic assembly (i.e., hard solders, glass- based die-attach materials, and the recently developed amalgams). Hard solders provide electrically conductive paths and have high thermal conductivity but are difficult to rework. ~ ./ They also require high-temperature processing conditions (depending on the alloy). They can be rigid and 55 brittle, causing cracking of a large die. Tests with Au/Si and Au/Ge have satisfactorily demonstrated small chip attachment (less than 9 mm on a side; Draper and Palmer, 1979~. The disadvantage of using hard solders stems primarily from their lack of plastic flow, which leads to high stress in the devices because of the thermal expansion mismatch between the die and the substrate. C.A. MacKay (1991) developed a new method of making a bonding amalgam that has potential for application in high-temperature electronics as die attach, hermetic sealing, and heat-sink die attachment. An amalgam is defined as a nonequilibrium, mechanically alloyed material formed between a liquid metal and a powder. In general, amalgams have low processing temperatures. Nevertheless, they still yield materials with thermal stabilities between 250 °C and 600 °C. The use of molytabs might provide a solution for reducing the high stresses that the hard solders impose on the system. In this technique, the die is preattached to gold-plated molybdenum tabs (molytabs) and then solder- attached to the tape automated bonded (TABed) die from the substrate bonding pads. The molytab, with a coefficient of thermal expansion of approximately 5 ppm/°C, forms a buffer between the device and the substrate.
Materials for High-Temperature Semiconductor Devices TABLE 5-3 Dielectrics for A1N Substrates Product designations Thermal expansion coefficient Dielectric constant Hi? 1 MHz) Dissipation factor (@ 1 MHz) Insulation resistance (100 VDC, 50 ,um thickness) Breakdown voltage (50 rim thickness) Adhesion to A1N Compatibility ESL# D-4907, ESL# D-4907-A 44 ~ 10-7/°C 5 - 7 0.5 - 0.8% > 10~ Q >2 kV Exceeds substrate fracture strength Most ESL Au and Ag conductors ESL# R-300 resistor series (when printed on the dielectric) Silver-glass-paste adhesives have also found an application in the assembly of high-temperature electronic devices. These materials are reflowed at temperatures of 400-450 °C. The glass recrystallizes during the reflow cycle and can subsequently be exposed to temperatures in excess of 400 °C (Johnson, in press). These materials offer the possibility of the formation of void-free, die-bond interfaces with excellent thermal stability. The tendency for silver migration and the effect of thermal cycling on the long-term adhesion of this system over extended temperature ranges has not yet been studied, however. Polymer die attach is normally not practical for use at temperatures above 250 °C where a nonconductive attachment is needed. However, silicone/polyimide adhesives can be made to operate effectively up to 400 °C. These materials offer the lowest cost when compared with the gold-based hard solders. The use of organic adhesives also supposedly lowers the thermal . ~ ~ stress in devices. However, the use of organic adhesives in high-temperature electronic packages has been limited because of outgassing and poor thermal stability (especially when filled with silver). INTERCONNECTION The typical interconnection methods used between chips and substrates are wire bonding, tape automated bonding, and flip-chip. Depending on the required operating temperature, the current interconnection methods may be limited by their material and mechanical properties for elevated temperature applications. Wires and bonds in a mono-metallic situation have been 56 evaluated for temperatures as high as 500 °C for up to thousands of hours and appear to be relatively trouble-free for either Au-Au or Al-A1 (Herman, in press). The application of parallel-gap welding for bonding of 5-mil annealed platinum wire to a 5,000 A platinum pad (with an underlying base of titanium, molybdenum, and 7 ., 7 tungsten) sputter-deposited on a sapphire substrate has been successfully developed for a high-temperature interconnect (800-1000 °C) for a thermionic integrated circuit (a vacuum integrated circuit technology; Fendrock and Hong, 19901. Problems arise when dissimilar metals are joined. For example, in case of Au-A1 intermetallic compounds, Kirkendall voids can form, weakening the interface. Another area of concern is the thermally induced change that can take place within some metallic materials themselves (Herman, in press). Two examples are reconstruction and creep in solders and crystallographic and electromigration changes in thin aluminum films and wire. Solders may be reliably operated at temperatures close to their melting point. Either substitute materials must be developed (for flip-chip) or all connections including package leads to the board must be welded either by using thermocompression or thermosonic methods (Johnson, in press). For example, the gold bumps in TAB provide connections between the aluminum pads (separated by a barrier metal to prevent diffusion and intermetallic formation at Al/Au interface) and the copper tape. These inner lead connections are made using a thermocompression technique. For outer lead bonding some type of welding is recommended. Exposed copper metal on tape should be completely plated with gold to avoid copper oxidation. While this technology shows great promise for high-temperature electronic applications, OTT · ~ ,J
High-Temperature Electronic Packaging TABLE 5~ Summary of Properties of Metall~zations for A1N Wirebondable Conductors FX 30-010 FX-30-011 FX-30-022 FX-30-023 Metallurgy Gold Au/Pd Gold Au/Pd Application Multilayer Multilayer Single layer Single layer Wire type Gold Silver Gold Al Resistivity 2.5-3.5 4.0-5.5 2.5-3.0 4-5 (mQ/O at 1 mil) Wirebond strength (g) 9-11 11-13 10-12 12-14 Thermal conductivity 180 180 180 180 W/m~~K~~ Solderable Conductors FX 34-100 FX 31-012 Metallurgy Ag/Pd Pt/Au Resistivity 13-16 16-181 (mQ/C~ at 1 mil) Solderability (seconds to 100% 1 1 coverage in 60/40 Sn/Pb) Solder leach resistance 25-30 20 (1 s dips to 80% retained) 90° peel adhesion (1 lb on 80 mil x 80 mil pad) Initial 10-14 8-13 Aged (150 °C, 48 furs) 8-10 2 bumped die and tapes are not readily available in the United States. SECOND-LEVEL PACKAGING Traditional packaging solutions for high-temperature applications have usually depended on inorganic substrates (e.g., alumina) and refractory metal conductors (e.g., tungsten and molybdenum). Since these materials require processing temperatures in excess of 1000 °C, their performance at high operating temperatures is inherent. The connections to these refractory conductors must also tolerate the operating environment and are therefore formed by welding, brazing, or high-temperature 57 soldering (i.e., metal-loaded glass frit solder). Selection of materials for these connections must accommodate the increased diffusion caused by long-term, high-temperature operation. Recent advances in organic dielectrics have allowed some application of organic, printed circuit boards in high-temperature environments, primarily for reduced cost. Polyimide printed circuit boards patterned with nickel, nickel-plated copper, or nickel-plated tin are common combinations. The bondability of nickel for welding or soldering is often improved by the selective deposition of gold over the bond sites. Some applications, however, require the use of large very-large-scale-integrated (VLSI) devices that would be unreliable if attached to substrates with significantly
Materials for High-Temperature Semiconductor Devices TABLE 5-5 Typical Cofired Metals Electrical Thermal Melting PointResistivity Thermal Expansion Conductivity Metal (°C)(10-8 Q m) (10-7/°C) (W/m K) Silver 9601.6 197 418 Gold 10632.2 142 297 Copper 1083 1.7 170 397 Palladium 1552 10.8 110 71 Platinum 1774 10.6 90 71 Molybdenum 2625 5.2 50 146 Tungsten 3415 5.5 45 201 different coefficients of thermal expansion. In these applications, silicon, or other ceramics, is the substrate material of choice. Conductors of patterned tungsten are used, although aluminum can be used if sufficiently protected with a high-temperature dielectric such as phospho-silicate glass or silicon nitride. SUMMARY Although high-temperature wide bandgap devices are being developed, they can only be successfully implemented into commercial applications if the packaging technology is developed in parallel to provide a cost and performance advantage. Novel approaches should be examined based on the existing knowledge of advanced packaging technologies, especially multichip modules. All of the integrated circuit wide bandgap devices for high- temperature electronics that are being developed are of a lower density of integration than existing complementary metal-oxide-semiconductor (CMOS), silicon-on-insulator (SOI), or even GaAs devices. Although existing packaging technologies can support the operation of high-temperature electronic integrated circuits, SiC, A1N, and diamond technology for packaging applications should be examined since the use of these materials will minimize the thermal mismatch and reduce any resulting stresses. The utilization of diamond and AlN as dielectric materials for multilayer interconnects deposited either on cofired A1N or on blank A1N, SiC, and diamond substrates should also be a part of the investigation. The use of SiC-encapsulated semiconductor devices (as demonstrated by Dow Corning) should also be considered. This technology ensures a hermetic die, which is very important for the devices working at elevated temperatures because chemical , 58 reaction rates are much higher at these temperatures. SiC encapsulation should be examined in conjunction with area array connections. Area array connections, such as tungsten bumps overplated with nickel and gold or copper bumps, are more suitable for high-temperature electronics than the traditional PbSn flip-chip attachment method. Other metallurgical structures should also be examined. Although there is no immediate need for the implementation of flip-chip or multichip module technology in high-temperature electronic applications, the benefits of developing these technologies could substantially affect the cost and performance of high- temperature electronics. For example, when using high- temperature electronics in conjunction with multichip module technology, the reliability of the system is improved due to a reduction in the number of metallurgical connections. In multichip module packages, the signal travels directly from chip to chip, all within the protection of a hermetic environment (Figure 5-2; Pedder, 1988~. As an interim solution, the following packaging schemes that are based on existing packaging technologies can be used in the temperature ranges specified below: · For temperatures <200 °C nonhermetic with silicones metal (welding, AuSn, gold diffusion) ceramic (welding, AuSn, glass, gold diffusion); · For temperatures < 300 °C -metal (welding, AuSn, gold diffusion) ceramic (welding, AuSn, glass, gold diffusion);
High-Temperature Electronic Packaging 1 Wire-bond 9 f ' ~ ! / 2 Package 8 \ / /3 Leads 7 \ 4 Solder Joints 5 Circuit Board Single Chip Package Assembly 1 Wire-bond 2 \ it/ ~ ~ IF any 3 Silicon Substrate Multichip Module Assembly FIGURE 5-2 Reduction from rune to Tree electrical paw segments between two integrated circuits win multichip module technology. SOURCE: Pedder (1988). For temperatures <400 °C -metal (welding, gold diffusion) ceramic (welding, glass, gold diffusion); and For temperatures < 500 °C ceramic (welding, gold diffusion) -sealed chip technology: Si3N4, SiO2, diamond. While materials and processes exist to meet the packaging challenges of high-temperature electronics whenever the market can match its needs with the supplier, better packaging solutions can be developed for high-temperature electronic applications when more complex and powerful systems are required. The use of existing high-density multichip module designs can leverage the development of high-temperature electronic systems by careful selection of the material systems used. 59 There is not an upper temperature that should be feared by packaging engineers any more than by the device physicist (Johnson, in press). Since high-temperature electronic devices and systems may undergo large temperature excursions depending on their applications (e.g., jet engines and spacecraft), the material and electrical properties will change accordingly (Sampson and Mattox, 19911. This change will be accompanied by the structural stresses on the chip and its package that are caused by the different thermal coefficients of expansion. Therefore, there is a need for an electrical and mechanical simulation for the proposed circuit. Nevertheless, basic material properties (for example, intermetallic compounds) must be examined over the wide temperature range that may be encountered in high-temperature electronics on both the short-term and long-term high- temperature behavior of the materials systems used in assembly and packaging (Herman, in press).
