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Appendix A: Silicon as a High-Temperature Material Silicon is the dominant semiconductor material in use by the electronics industry today, but is generally not thought of as a high-temperature semiconductor material. Its comparatively narrow energy bandgap creates the majority of problems during high-temperature operation when attempting to use silicon material as a discrete device or in integrated circuits for digital, analog, or power applications. However, surveys of the literature indicate that silicon bipolar and complementary metal- oxide semiconductor (CMOS) analog and digital products can function adequately beyond the MIL SPEC limit of 125 C. Circuit and layout techniques can extend the reliable temperature range of conventional bulk CMOS and bipolar to at least 200 C, while a combination of bi- CMOS, conservative layout rules, supply voltage reduc- tion, and scaling of transistor (channel) dimensions can extend the range to 250 C. The further addition of oxide- isolated processes can extend silicon bipolar and CMOS circuitry to 300 C by reducing leakage currents, parasitic capacitances, and threshold voltage-dependence on temperature. General high-temperature issues for semicon- ductors, which also pertain to silicon, are discussed in Chapter 3. This appendix begins with a description of high-temperature performance of several silicon technolo- gies, then moves on to a consideration of oxide-isolation processes that can extend the functional temperature range of silicon circuits. HIGH-TEMPERATI)RE OPERATION OF SILICON CIRCUITS Bipolar Analog Circuits Historically, operational amplifiers have been the most-studied bipolar analog integrated circuit. The changes in bipolar component characteristics mentioned 81 above can be so great with respect to temperature that conventional design methods cannot be used; in fact, design compensation techniques may be only valid for limited temperature ranges. Leakage currents must be compensated for in all designs; for example, the base- collector leakage current, ICbo, flows in the opposite direction to the normal base current and can become larger than the normal base current as operating tempera- tures increase, reducing the base current necessary to sustain collector current. Decreases in base-emitter voltage, Vbe (less than 100 mV), can force devices to go into saturation; current design must be used to compensate for this unintentional saturation. In general, large changes in parameters such as Vbe and diffused resistor values of the base and collector cause problems in obtaining controlled and constant circuit performance over wide ranges (Beasom and Patterson, 1982~. These parameter changes manifest themselves as failures due to degradation in the input-offset voltage, VOS, the open-loop gain, and the bias current. Bipolar Digital Circuits Commercial four-input standard and Schottky-clamped TTL NAND gates were tested from 25-325 C. The high- temperature [allure modes of both TTL NAND gates were identical. The functional failure mode was low output-high voltage, Voh, and contributed to the collector-base leakage current (from the phase splitter transistor) flowing through the phase splitter collector resistor. The voltage drop across the collector due to the excess leakage resulted in a decrease in Voh. The power-supply currents for output- high and output remained stable through 300 C. Current- sinking capability increased as the temperature was increased due to the increasing gain of the current-sink transistor. Current-sourcing capability was reduced due to

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Materials for High-Temperature Semiconductor Devices the increase in circuit resistance values (Prince et al., 1980). FET Analog Circuits Design techniques for high-temperature analog CMOS generally try to address the temperature dependence of mobility, drain current, threshold voltage, and leakage currents of MOS transistors as a first attempt to increase the range of temperature operation. Observed effects in analog CMOS circuits due to changes in transistor parameters include: (1) a decrease in amplifier-gain bandwidth product and gain, (2) an increase in amplifier input-offset voltages, (3) bias point shifts, and (4) a de- crease in sampling rate due to leaky switches. For a simple two-stage CMOS operational amplifier, design techniques have been used to allow the op amp to function up to 250 C. The most important design technique used was to bias the two gain stages and the output stage at their zero temperature coefficient (ZTC) drain currents in the saturation region (e.g., ZTC is a gate-bias voltage at which the drain current exhibits minimum temperature sensitivity). The ZTC gate bias was applied to the current source biasing each gain stage and to the n-MOS of the output stage by using a voltage divid- ing string composed of n- and p-MOSFETs. Leakage currents were compensated for by cascading n- and p- MOSFETs or by using compensation diodes. Cascading was used in the voltage dividing string and the output stage. Cascading of n- and p-MOSFETs to a common circuit node allows the leakage currents from the drain to body of the n-MOS and the source to body of the p-MOS to cancel each other with appropriate selection of MOS- feature sizes. For the differential input stage, a compensa- tion diode can be placed at any node where the use of cascaded MOS pairs is not possible; the diode can then be used to shunt excess current to one of the power rails (Shoucair, 19861. Digital CMOS General high-temperature effects observed for digital CMOS include: (~) decreasing noise margins and (2) decreasing switching speeds. CMOS type 4012 NAND circuits were tested from 25-300 C, with acceptable performance noted to 270 C. Leakage current on the p- well-substrate junction was determined to limit circuit 82 functionality. The output-low voltage, VO', increased at high temperatures due to the inability of the e-channel transistors to sink the leakage currents generated at high temperature. Change in threshold voltages also altered the logic threshold of the voltage transfer characteristics (Prince et al., 19801. Additional layout (e.g., guardrings or larger n-MOS/p-MOS separation) or processing techniques (e.g., epitaxial substrates or trenches) may be required to suppress latchup at higher temperatures (Estreich and Dutton, 1982~. DIELECTRIC ISOLATION TECHNOLOGY Leakage current in reverse-biased junctions is one of the major problems with the operation of junction-based devices and junction-isolated integrated circuits (ICs) at high temperatures. In bulk CMOS, large junction areas exist between the source, the drain, and the p-well, and between the p-well and the substrate. For junction-isolated bipolar, large junction areas exist between the collector well and the substrate. As described above, junction- isolated circuits with no special design precautions for high temperatures can fail at temperatures as low as 200 C. The use of dielectric isolation (DI) or silicon-on- insulator (SOI) eliminates the problem of junction isola- tion in Ics by isolating each device with an oxide layer that will (1) eliminate parasitic leakage currents between devices and between devices and power rails, and (2) eliminate extra junctions that form parasitic devices. The primary benefit of SOI use for CMOS and some bipolar ICs is the elimination of latchup. SOI eliminates the formation of parasitic p-MOS devices in bipolar ICs and the formation of parasitic bipolars in CMOS ICs. Figure A-1 illustrates the reduction in large junction-isolation areas by the use of trenches and SOI. SOI also allows MOS devices to be fabricated in a manner that reduces leakage currents within the MOS device itself. The silicon film can be made thin enough to allow the drain and source wells to contact the dielectric layer; the junction area between the source or drain and the channel is the width of the FET multiplied by the thickness of the silicon film. Reducing the thickness of the silicon film can lead to an SOI FET with leakage currents that are orders of magnitude smaller than in a bulk FET. Figure A-2 illustrates the leakage current as a function of

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Appendix A: Silicon as a High-Temperature Material Standard Bipolar P+ N+ N+ P+ N+ P P+ 1 1 1 1 1 1 1 ",' ~ ~ " .' Si Substrate . Bipolar/SIMOX Trench N+ N+ P+ N+ P Trench 1 1 1 1 1 1 1 I ~ r I \~` 1 1 Buried Oxide _ Si Substrate FIGURE A-l Reduction in large junction isolation areas by the use of trenches and SOI. SOURCE: Ibis Technology Corp. (l99l). temperature for three types of n-MOS transistors with gate lengths of 2 microns. Leakage currents in thin-film transistors may not be linearly dependent on the silicon film thickness; theoretical calculations show that the leakage current decreases more rapidly as the thickness is decreased. Parasitic capacitances are also reduced by reduction of those junction areas (Swonger et al., 1991~. While the use of SOI in bipolar devices does reduce isolation, latchup, and parasitic MOS-device problems due to leakage currents at high temperatures, problems such as Vbe reduction, transistor current gain, base current reversal, etc., still remain. These problems can be successfully addressed through circuit and device layout modifications. DI techniques commercially used today include: (1) separation by implantation of oxygen (SIMOX); (2) wafer bonding, lapping, and etch back; and (3) V-groove etching, polysilicon filling, and lapping of the crystalline . ~ silicon. Wafer Bonding - Wafer bonding is the latest SOI technology. Bonded wafer substrates can be prepared by thermally oxidizing two wafers. The wafers are then treated so that the oxide surfaces become hydrophilic. The oxide surfaces are then placed face-to-face, forming a weak room-temperature bond. Subsequent annealing at temperatures greater than 800 C form stronger bonds so that the wafers can no longer be separated. After bonding, one of the walers (the 83 device wafer) is thinned to the desired silicon film thickness by grinding, electrochemical etching, and polishing. Thin and uniform silicon layers are difficult to produce using the wafer-bonding technique (Swonger et al., 1991~. Wafer bonding is currently limited to silicon film thicknesses larger than 1 Em due to thickness varia- tions of 0.5 ,um during thinning processes. Wafer-bonding does provide an excellent quality silicon film with very few dislocations. The wafer-bonding process also facili- tates the fabrication of SOI wafers with very thick buried oxide layers. The high-quality silicon films and thick oxides generally make wafer bonding a good technology for high-performance bipolar applications. Dislocations can cut through the bipolar emitter and collector, allowing preferential diffusion and punch-through. Thicker oxide layers reduce substrate capacitance, allowing higher-speed bipolar performance. Sl:MOX In the SIMOX process, a buried SiO2 layer is formed below the silicon wafer surface by implanting oxygen into the wafer at sufficient dose and energy. The thickness and quality of the silicon and SiO2 layers depend on the oxygen dose, temperature of the wafer during implanta- tion, and anneal temperature after the implant. Multiple implants are used to reduce the silicon defect density. As an example, a high-quality sample was made with a 400- nm-thick buried oxide and a single-cr~rstal 250-nm-thick silicon top film. The ion dose, energy, and implantation temperature were 1.8 x 10~8 amp, 200 keV, and 620 C, respectively. A final post-implant anneal of 1350 C was used. The quality is adequate enough to fabricate 256 k 10-5 106 107 10-8 10-9 -10 -l1 - Thick SOI (40~ I 1 1 1 1 1 1 1 1 1 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 1 000/T(K) FIGURE A-2 Leakage currents as function of temperature for three types of n-MOS transistors with gate lengths of 2 microns. SOURCE: Swonger et al. (l99l).

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Materials for High-Temperature Semiconductor Devices SRAMS. Commercial vendors offer SIMOX wafers from increased as temperature increased while the open-loop 3 in. to 200 mm diameter. SIMOX is traditionally used gain decreased with increasing temperature; this latter for CMOS applications instead of wafer bonding because parameter is shown in Figure A-4 as a function of thin and uniform layers can be produced (Colinge, 19931. temperature. It was reported that degradation could be minimized by incorporating other high-temperature design techniques into the operational amplifier design. Lateral Isolation In addition to vertical isolation processes afforded by the SOI technology, a lateral isolation process is needed to isolate devices. In SOI, thin silicon films can be etched off between devices or consumed by local oxidation. Lateral isolation in thick films is obtained by etching narrow and deep trenches through the silicon layer to the buried oxide layer. These trenches can then be filled with an oxide. APPLICATIONS TO DEVICE TECHNOLOGY P Bipolar-Junction-Transistor Applications in SOI Technology Recently, lateral n-p-n bipolar transistors have been fabricated using SIMOX SOI substrates. The bipolar structures were investigated for high-frequency and smart- power applications and no high-temperature tests were mentioned, although the benefits of dielectric isolation with respect to higher integration density, no latchup, less leakage current, high-temperature operation, and noise immunity were mentioned (Weyers et al., 1992; Parke et al., 1993). Operational amplifiers that used dielectrically isolated bipolar transistors and other design techniques mentioned above were developed in the late 1970s by Harris (Bea- som and Patterson, 1982~. The operational amplifier was characterized over the temperature range of 25-300 C. Useful circuit performance was observed up to 300 C. In Appendix C, Table C-1 summarizes the electrical parame- ters of the 300 C op amp. A similar op amp circuit design was refabricated by Harris using a DI process flow and bonded wafer SOI substrates (Swonger et al., 19911. The process flows are shown in Figure A-3. Other than dielectric isolation, no other high-temperature compensa- tion techniques were used for this circuit design. These op amps were also tested to 300 C, with all devices func- tional to that temperature. Power dissipation, input-offset voltage, input-bias current, and input-offset current 84 CMOS Applications in SOI A variety of CMOS circuits based on SOI has been tested for high-temperature applications. Circuits tested include inverters, 19 stage ring oscillators, and 4 k through 128 k SRAMS. Allied Signal has tested thick- and thin-film MOS- FET-based inverter circuits to temperatures as high as Dielectric Isolation Bonded Wafer N . ~__) N+ N- . ~ ' N+ r b N- | ; ~ ''' ''I'"<-" - ''" , _ 2 . a ~ rim ~, _ \~ N+ J N- ~ ~ 7~/~/~/~//r~///~//// / .. ,,. ~ b N+ ) N- ~ P+ J -Y~,,,f ,,~x,w,+, it._ _~ tf~ ~,~,,,,' J .,~,,, J ~ c ~ POLY OXIDE ~ l . . IN+= N N+ + d d . N ~ P- l I N+ ) ~ P+ ~, ~ 1 ~ '~ ~ ~ ~ ,, _~/ in, ., e POLY FIGURE A-3 Schematics of the dielectric isolation material process flow and the bonded wafer material process flow. SOURCE: Swonger et al. (1991).

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Appends A: Silicon as a High-Temperature Material Too m ~ 90 > c ._ o c o 80 70 60 50 Bonded Wafer . 1 1 0 50 100 Dielectnc Isolation 150 200 250 300 350 Temperature (C) FIGURE A-4 Open-loop gain as a function of temperature. SOURCE: Swonger et al. (1991). 450 C. The leakage current is greatly reduced by the use of SOI with two films. Inverters made in 4,000-A-thick SOI were tested to 450 C with fairly good results. Leakage currents did degrade their noise margin some- what, and threshold voltage shifts did change the output- voltage versus input-voltage swing slightly (McKitterick, 1991). Harris has tested 4 k SRAMs in silicon and SOI from 25-300 C. The SOI SRAMs functioned to 300 C, with degradation occurring in access times and circuit standby current. The bulk SRAMs failed at 275 C. SOI SRAMs (64 k) developed for military applica- tions by Honeywell have been tested at 250 C for 5,000 hours. The SOI CMOS process tested has not been optimized for high-temperature operation but is being modified to develop an SOI process capable of 300 C operation. Digital products to be tested include processors and application-specific ICs as well as memories. Linear products in development for high-temperature testing include operational amplifiers, analog switches, voltage references, and application-specific integrated circuits. REFERENCES Beasom, J.D., and R.B. Patterson. 1982. Process charac- teristics and design methods for a 300 C quadoperational amplifier. IEEE Transactions on Industrial Electronics IE-29~21: 112-117. Colinge, J.P. 1993. SOI Technology: Materials to VLSI. Amsterdam, Netherlands: Klewer Academic. Estreich, D.B., and R.W. Dutton. 1982. Modeling latch- up in CMOS integrated circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD-14: 157-162. Ibis Technology Corporation. 1991. SIMOX for high temperature applications. Ibis Technology Application Note, No. 103. Danvers, Massachusetts: Ibis Tech- nology Corporation. McKitterick, J.B. 1991. Very thin silicon-on-insulator devices for CMOS at 500 C. Pp. 37-41 in Proceed- ings of the First International High Temperature Electronics Conference, Albuquerque, New Mexico, June 16-20. Parke, S.A, C.M. Hu, and P.K. Ku. 1993. A high- performance lateral bipolar-transistor fabricated on Si MOX. IEEE Electron Device Letters 14~11:33-35. Prince J.L., B.L. Draper, E.A. Rapp, J.N. Kronberg, and L.T. Fitch. 1980. Performance of digital-inte- grated-circuit technologies at very high temperatures. IEEE Transactions on Components, Hybrids, and Manufacturing Technology CHMT-3~4~:571-579. Shoucair, F.S. 1986. Design considerations in high temperature analog CMOS integrated-circuits. IEEE Transactions on Components, Hybrids, and Manufac- turing Technology 9~31:242-251. Swonger, J.W., S.J. Gaul, and P.L. Heedley. 1991. An evaluation of amp performance up to 300 C using dielectric isolation and bonded wafer material tech- nologies. Pp. 281-290 in Proceedings of the First International High Temperature Electronics Confer- ence, Albuquerque, New Mexico, June 16-20. Weyers, J., H. Vogt, M. Berger, W. Mach, B. Mutter- lein, M. Raab, F. Richter, and F. Vogt. 1992. Microelectronic Engineering 19~1-4~:733-736. 85

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