of growth of the industries it serves.2 Projections are that by the end of the decade, sales of equipment for plasma etching, cleaning, physical vapor deposition (PVD), and chemical vapor deposition (CVD) will reach $10 billion.3 An important trend in the industry is the rapidly escalating cost of capital equipment, and the growing share of equipment costs (now about 60%) in the total cost of a state-of-the-art fabrication facility (currently about $1.5 billion).4

The projected changes in integrated circuit technology anticipated in the 1994 roadmap of the Semiconductor Industry Association (SIA) are given in Table 1.1. The historic trend of a doubling in device density every 1.5 years or so will continue. New generations of technology are introduced every 3 years, fueled by information age demands that continue to explode. Notably, the introduction of 0.25 µm technology overlaps the introduction of the next jump in wafer size to 300 mm diameter in 1999. Part of the reason for the exceptional rate of growth in the semiconductor industry has been the dramatic and steady rise in performance per unit cost. In order that this trend in the performance/cost ratio continue, the next-generation developments listed above must be accomplished with a corresponding increase in manufacturing efficiency.

TABLE 1.1 Changes in Silicon Integrated Circuit Technology Projected to 1999






Critical dimension (µm)





DRAM capacity (Mbits)a





MPU/logic clock speed (MHz)b





Wafer size (mm)





Defect density (no./cm2)





Interconnect levels





a DRAM = dynamic random access memory. b MPU = microprocessor unit.

SOURCE: A. Voshchenkov, Workshop on Database Needs in Plasma Processing, Washington, D.C., April 1-2, 1995.

Increasing manufacturing efficiency will require a significant increase in the sophistication and effectiveness of process control, among other changes. For example, as critical dimension (CD) decreases, the control of the CD must be to within 0.03 µm. Even though the wafer diameter will increase, etching rate and selectivity nonuniformity across the wafer must in some cases be kept to less than 2%. During etching, an important control variable is the angle of the microfeature sidewall with respect to the surface. Control of this profile angle is sought to within 3 degrees. Another important processing variable in MOSFET (metal oxide semiconductor field effect transistor) manufacturing is related to the thin (<< 80 Å) gate oxide between the gate electrode and the active device region below it. During the etching step in which the gate electrode is defined, and when gate oxide may be exposed to the plasma, selectivity must be high enough to keep gate oxide loss to less than 15 Å. This is only 4 to 5 atomic layers.

From the industrial perspective, plasma processing, especially plasma etching, is often seen as being unusually difficult to understand and control.5 Although some of the general mechanisms of the plasma are known—such as the role of chemical interactions with radicals such as F or C1 atoms, the role of sidewall passivation in preserving etch anisotropy, and the fact that positive ion bombardment of surfaces has a mechanical sputtering role—many details remain obscure. Interactions between plasma species and the walls bounding the discharge are complex and depend on surface temperature, surface and bulk composition, and other variables that are empirically observed to change with time, but are not well understood. The goals of plasma etching, including high rate, selectivity, uniformity, minimal damage to the underlying nascent electrical devices, minimal chemical residue contamination, minimal particulate deposition, and microfeature critical dimension control, sometimes depend in subtle ways on the plasma quantities. Moreover, these processing objectives are commonly difficult to achieve simultaneously. For example, there is often a conflict between etch anisotropy (enhanced by more energetic ion bombardment)

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