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Energy-Efficient Technologies for the Dismounted Soldier 4 Low Power Electronics and Design The dismounted soldier depends on power sources, sensors, navigation aids, displays, data processing, and communications. Communications requires the most power, but substantial energy savings can be obtained by minimizing the power requirements for individual display data processing, and sensing functions. This chapter reviews ways to use advanced electronics technology to reduce energy consumption. It summarizes industry trends and projections and indicates some of the advantages of synchronizing military and commercial electronics to leverage the huge industrial investment. The growing industrial need for creating, accessing, storing, processing, and communicating information is driven by modern business functions and by the growing demands of consumers for data acquisition, processing, and entertainment. The trend originated with the advent of the electronic calculator, the personal computer, and microprocessor-driven games. Although at first stationary electronics systems were used, the industry has moved toward mobile systems, which require lightweight portable energy sources and equipment. Portable commercial and personal communications and data processing have evolved from crude hand-held instruments and bulky laptop computers to miniaturized cellular telephones and pagers, powerful notebook computers, portable global locating/positioning systems, and numerous entertainment systems. The growing demand for computing, along with declining costs, has led to faster, smaller, more reliable integrated circuits that require less power. The technology accompanying these advances can be incorporated into the soldier's electronics systems to make them more functional and to reduce power requirements. This chapter focuses on the development of advanced semiconductor circuits with an emphasis on silicon technology. Industry has embarked on a long-range plan to reduce the size and operating voltages of electronic devices and to increase the integration of devices and circuits. The Army can use this same plan to schedule its own electronics goals. The chapter begins with comments on the design of basic circuits, subsystems, and design aids to minimize power. It reviews the National Technology Roadmap for Semiconductors (NTRS) for technology development. To show that industry goals are attainable, the committee presents its own
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Energy-Efficient Technologies for the Dismounted Soldier analysis of the ultimate limits for miniaturization and integration density for silicon circuits. Three representative examples of special support centers, conferences, and studies or programs that can serve the Army as sources of state of the art design and technology information on low power circuits and subsystems are then described. The chapter summary suggests issues the Army should address (1) to ensure that adequate design tools are available for implementing low power circuits and technology, (2) to support industry in following the road map toward continued power reductions, (3) to keep abreast of state of the art technology, and (4) to field technology in phase with industry. The committee estimates that if the Army upgraded technology at a pace comparable with the pace of industry, it could reduce power requirements by more than a factor of 30 for any given function by migrating from 5V operation to 0.9 V operation in 2004. Additional reductions could be obtained by tailoring circuit architecture and designing for low power. DESIGN REQUIREMENTS The commercial push toward smaller, higher performance portable systems for computing and personal communications will ensure that low power device and circuit technologies will be available to meet the requirements of the soldier system. However, to exploit those technologies the Army must take full advantage of advances in commercial technology (including using modules, which permit upgrading system elements to prevent obsolescence), and it must adopt customized and partly customized designs optimized for power (with sufficient performance) rather than optimizing for performance (with acceptable power requirements). A full set of computer-aided design (CAD) tools for estimating and optimizing power requirements does not exist, and developing these tools may require a new U.S. Department of Defense (DoD) initiative. Digital Guidelines For complementary metal-oxide semiconductor (CMOS) technology, the dominant digital technology, the approximate power dissipated by a circuit is given by the following expression (Chandrakasan and Brodersen, 1995a): P = A·C·f·V2 + A·Isw·V + Ileak·V + Pext (1) A = percentage activity factor. C = total chip capacitance (farads). V = total voltage swing, usually near the power supply voltage (volts). f = chip clock frequency (Hz). Isw = average short circuit switching current (amperes), current when both p-type metal-oxide semiconductor (PMOS) and n-type metal-oxide semiconductor (NMOS) are on simultaneously during a logic change. I leak =
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Energy-Efficient Technologies for the Dismounted Soldier leakage current (amperes) from substrate injection and subthreshold effects. Pext = power required to drive external loads, such as package parameters, chip-to-chip interconnects, etc. The total power (P) can clearly be minimized by lowering the total voltage (V). Lower voltages will be a natural result of smaller feature sizes operating at lower voltages. Voltage can be further reduced for fixed minimum geometries. However, device speed decreases dramatically as the voltage approaches the threshold voltage, which is acceptable only as long as performance goals can be met. Threshold voltages can be lowered as long as adequate noise margins are maintained and as long as subthreshold currents do not increase energy dissipation. Capacitance will also be reduced as feature sizes shrink. The effective capacitance (A · C) can be further reduced by modifying the design. For example, because energy is dissipated only during transitions, logic functions can be chosen to minimize transitions. Similarly, logic style (such as static versus dynamic implementations) can be selected to minimize transitions, including the extra transitions or ''glitches" caused by timing delays between logic signals. The second term in the equation (A · Isw · V) results from energy dissipated in the direct current path between V and ground, which exists briefly during switching when the difference between V and the PMOS threshold voltage exceeds the NMOS threshold voltage. Short circuit currents are largest when the rise/fall time at the gate input is much larger than at the output. Currents can be minimized by equalizing input and output edge times. The third term in the equation (Ileak · V) arises from energy dissipated due to leakage current, which has two components. The first is the reverse bias diode leakage on the transistor drains, which, although small for each gate, can have a significant impact on a system that is predominately in the standby state because it dissipates energy even in the absence of switching. The second component of leakage current is subthreshold leakage, which is caused by carrier diffusion between source and drain. These leakage current components are a function of the device implementation, which is affected by the semiconductor fabrication technology. The first term in Equation (1) (A · C · f · V2) is a measure of the device performance and represents the charge transferred to the circuit load capacitance. For maximum efficiency and performance, the product of C · f · V, which is known as the charging current (Idrive), should be high. At the same time, the leakage currents should be minimized. The drive current is a function of the supply voltage (V) and the transistor threshold voltage, which is determined by the technology. Although a detailed discussion of the relationship of threshold voltage to Idrive, Isw, and Ileak is beyond the scope of this report, it should be noted that by tailoring the technology manufacturing parameters, Idrive can be increased while Isw and Ileak are minimized. Therefore, a simply stated goal for optimizing performance and reducing the power requirements is to maximize the ratio
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Energy-Efficient Technologies for the Dismounted Soldier (Idrive/Ileak) at the transistor device level. Power loss is minimized by using technologies that allow selecting the transistor threshold voltages, tailoring the transistor drive current to the load, and at the same time minimizing the leakage current. The optimum threshold voltage must balance improvements of the drive current at low supply voltage operation with control of leakage currents. Silicon on insulator (SOI) technologies, including silicon on sapphire with thin silicon conducting layers, can be optimized this way. DARPA has sponsored a number of similar projects on the development of low power circuits (Lemnios, 1996). System Architecture Modifications of design and system architectures can also save energy, as appropriate to a given system. For example, gated clocks should be used wherever possible, although they may complicate timing analysis. Some specific algorithms and software are more efficient than others from a power perspective (e.g., Grey's Code can require less power than "two's complement" for specific applications), and power-down routines should be used wherever possible. Logic partitioning and architecture can be chosen to optimize energy savings rather than speed; for example, a carry look ahead adder is fast, but a ripple carry adder may dissipate less energy. Large benefits can be realized by customizing layouts for minimal capacitance. When power is a priority, the capacitance of the interconnect must be considered along with the capacitance of the device. Routing should be kept as short as possible, especially on the most active paths. Full custom circuits are better than standard cell and gate array designs, but they shift more of the burden to the designer and lengthen the design process. Combinations of these techniques or new architectures can minimize load capacitance and standby power and optimize supply voltage for circuit sections. Significant energy savings can be made by choosing the proper input/output (I/O) and package design. Circuit I/O should be minimized to reduce the number of energy-consuming drivers; in some situations, for example, it is more efficient to recompute data than to retrieve it from off chip. In some instances, computational results can be stored in local memory to minimize energy-consuming external memory accesses. Using multichip modules (MCMs) can also reduce the power required to drive long signal lines. The guiding principle should be that as much of the system as possible should be included in a single package, whether the package is a chip or a module. In general, new packaging techniques will be required to minimize interconnect capacitance for low power applications. The preceding is not an exhaustive list of the design and architectural measures that can be taken to reduce power requirements. Some of these measures make small contributions when considered in isolation; but when power considerations drive all aspects of circuit and system design, the total savings in the volume and weight of the equipment that must be carried by the individual
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Energy-Efficient Technologies for the Dismounted Soldier soldier can be significant. And savings to the Army in the requirements for portable power sources can be enormous. Analog and Radio Frequency Design Recent advances in CMOS radio frequency (RF) circuits have demonstrated that circuit building blocks, including entire transceivers (Abidi et al., 1997) can be designed to enable fabrication of mixed analog-digital radios on a single chip. Integrated circuit designs have been demonstrated using 1 µm channel lengths and operating at 900 MHz; 0.6 µm channel length devices can operate in the 2.4 GHz range. Scaling feature sizes to 0.35 µm or less will make possible operational frequencies of 5 GHz. These designs have demonstrated that digital circuits can be fabricated on the same substrate as the RF front end, that there is enough on-chip isolation in a low cost package to guarantee stable operation of a receiver with more than 100 dB of base-band gain, and that the power amplifier, when switched across the full output range, modulates the unlocked local oscillator frequency by about 220 parts per million. A complete noise analysis indicates that the noise level is well below the detector pass-band. These RF analog circuits have demonstrated the capability of switched-capacitor circuits to handle large signals without distortion, the ability to cancel quadratic nonlinearity in balanced circuits, the use of field effect transistor switches to compute signals at RF, and the large signal swings possible in a transistor with an insulating gate. Advanced RF circuits demonstrate that CMOS circuits can be used in low power, low cost transceivers. The Army could use a mix of digital and analog circuits and still take advantage of the improvements in performance and energy consumption afforded by CMOS technology. The future design of RF circuits, including transceivers for low power, will follow many of the guidelines used for other types of circuits. Circuits can be turned on only during receive and transmit times to minimize the number of circuits that are powered at any given time. Transmission power and bandwidth can be tailored dynamically to meet specific needs. The lowest practical voltage consistent with noise immunity can be used for each section of the system. Circuits can be customized to use special technologies as required, implementing logic and control in CMOS, for example, while using silicon-germanium (SiGe), gallium-arsenide (GaAs) or silicon on an insulating substrate for special RF circuit modules. In addition, the subsystem design can be customized to meet specific mission requirements. The SiGe heterojunction bipolar transistor technology (Cressler et al., 1994) combines the performance historically associated with compound semiconductor technologies (such as GaAs) with the integration levels, yield, and cost associated with conventional silicon processing. SiGe transistors can be integrated with advanced CMOS processes because they are more scaleable and easier to manufacture than GaAs. SiGe transistors may also give the Army more flexibility in managing power requirements. The SiGe technology in logic circuits
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Energy-Efficient Technologies for the Dismounted Soldier has demonstrated sub-20 ps delays, and individual transistors have exhibited cutoff frequencies in excess of 100 GHz. These high switching speeds can support the RF needs for the soldier's radio communications. Examples of Circuit Design Actual circuit designs employ a variety of techniques to minimize power requirements at the system level. For example, to achieve maximum energy efficiency for mobile electronics, a number of voltage levels are usually required from a fixed battery source. Special attention must therefore be paid to voltage conversion circuits. There are several choices of design and type of voltage converter that can minimize the required power. Similar examples can be found for implementing computing circuits, portable telephones and radios, displays, and other systems described elsewhere in this report. DESIGN AIDS FOR LOW POWER INTEGRATED CIRCUITS One of the capabilities that has enabled the rapid increase in the complexity of integrated circuits has been the development of efficient CAD (computer-aided design) tools. These tools support the synthesis of complex circuit functions; the simulation of the basic circuits; the design of mask geometries supporting circuit manufacture; the accurate simulation of circuit modules, subsystems, and complete circuits (including layout and process effects); and the testing of finished circuits. The traditional driving forces in developing new CAD tools have been more complex circuits, improved packing density on the silicon, higher performance circuits, self-testing circuit modules, and better automation of the design process. In terms of silicon efficiency, development has focused on surface area and performance. In general, CAD tools that focus on reducing power have not been developed. New CAD tools are needed so that each parameter in Equation (1) can be considered in the design and implementation of specific circuit functions. The design process can be divided into the following levels (from highest to most detailed): behavioral, architectural, logic, circuit, and physical (Singh et al., 1994). For low power system design, power minimization methods must be built into the CAD tools at each step. At each design level, the power required must be estimated for a specific application to establish a set of energy conditions as a function of the design alternatives. For low power design, the entire design sequence must be an iterative process, in which the exact power requirement depends on the implementation, which influences higher level design decisions.
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Energy-Efficient Technologies for the Dismounted Soldier Behavioral and Architectural Level Design At the behavioral level, algorithms and system partitions are selected based on system use. System partitioning can be influenced by the activity level of circuit use and subsystem operating frequency and voltage. Architectural level design consists of mapping and implementing the functional building blocks into hardware building blocks consisting of registers, busses, data paths, and functional blocks representing such things as executing units, controllers, and memories. Often the behavioral and architectural design steps are so closely interrelated (because of the design hierarchy, data flow, and control) that they are combined and optimized together. In this case, system simulation is performed at the functional level to ensure adequate or consistent definition of the functional blocks and interfaces. At the behavioral and architectural design level, tools will be needed to enable designers to explore, evaluate, compare, and optimize power dissipation alternatives early in the design process. Switching activity and the required operating voltage level for each circuit block can affect the power requirement. Switching activity is a function of the applied data and algorithms and is usually based on extensive simulation using empirical data. At the system level, substantial energy savings can be achieved by identifying common sections of circuitry that can operate at reduced voltage levels. For lower voltage operation, performance compensation can be regained by using special transistors sized for the signal or by implementing concurrency at the architectural level. At the architectural level, energy savings can be obtained by optimizing the instruction set or using a hardware module to implement a specific data path to execute a specific instruction. Chandrakasan and Brodersen (1995b) present a strategy for voltage scaling in which concurrent architectures are used to retain throughput at reduced supply voltages. In this approach, parallel data paths are used, even though parallel paths and additional wiring increase the total capacitance and the parallel paths operate at slower speed. A similar power reduction can be obtained using parallel memory access with reduced clock rates, as compared to serial access. Logic Level Design Logic level design tools process the functional blocks defined at the architectural level, synthesizing the circuit implementation in terms of individual logic gates and switches. The logic level design strategy for power savings optimizes the circuit to obtain low switching activity for nodes that drive large capacitive loads. Power savings can also be obtained during logic synthesis by considering dynamic power dissipation involved with short circuit currents and slew rates, using accurate delay modeling, and matching equivalent signal pins within a specific gate library to minimize capacitive charging loads.
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Energy-Efficient Technologies for the Dismounted Soldier Circuit Level Design In the final circuit design step, logic gates are implemented at the circuit level, where individual transistors are designed with appropriate interconnections to perform the logic function. Simulation is used to model the detailed operation of the circuit and can be used to predict circuit performance and to calculate or verify the amount of power consumed in each area of the circuit. Physical Level Design Physical design usually refers to the design and layout of the individual masks describing each transistor and the interconnections required to implement each circuit module. During mask layout, the goal is to reduce the capacitive load associated with each switching node of the circuit. The capacitance can be minimized by optimally sizing each transistor and interconnect. At the highest level of layout, power minimization must be performed by optimal circuit partitioning and chip floor planning, i.e., geometric placement of the various circuit blocks. At the lowest level, individual transistor gate sizes, transistor placements, and interconnect wire-widths must be tailored to minimize capacitance. At all levels, circuit performance and total circuit layout area must be included in the power optimization goal and appropriate trade-offs in the design. Special consideration should be given to the layout of the clock circuits because these circuits have the highest frequency and are distributed globally over the chip. The use of multiple clocks, with the switching frequencies optimized for specific functions, and the judicious use of power-down or sleep circuits can reduce energy consumption. At the integrated circuit design level, most physical design tools rely on a library of predefined and simulated cells to implement specific logic functions. These library elements are placed in pseudo-regular patterns and interconnected to implement the functional building blocks. Although many of the cells are manually designed to optimize compact layouts, interactive design tools can be used to simplify layout and analysis for individual logic cells. Floor planning and circuit partitioning can be used to optimize the layout to reduce power requirements by collecting various circuit and logic functions to minimize off-block capacitance and keep the high switching activity nets within the same block. Individual placement of cells is based on the signal frequency and associated net capacitance. During signal routing, higher priority is placed on reducing the length and capacitance of nets with high switching activity. Depending on the flexibility of the cell library, a power saving can often be realized by tailoring the size of the transistor drivers and the widths of the interconnects for specific nets to reduce total capacitance while maintaining a constant gate delay.
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Energy-Efficient Technologies for the Dismounted Soldier Meeting Unique Army Requirements All aspects of low power design are addressed in detail at special conferences and in the professional electrical engineering journals, such as journals published by the Institute of Electrical and Electronics Engineers (IEEE) and other publications cited in this chapter. Industry has reduced system power requirements for portable functions dramatically by moving from a simple pursuit of higher performance to a deliberate effort to minimize power. To build and adapt systems to meet its unique requirements, the Army will have to do the same for system, subsystem, and integrated circuit design methods. Contracts with commercial vendors should specify the use of energy-efficient techniques and technologies. If CAD tools that minimize power while minimizing manufacturing costs and maximizing reliability are not available commercially, the Army should support their development for each stage of the design process. INDUSTRY TRENDS Semiconductor technology has progressed at a phenomenal rate over the past 30 years. Based on the early development of integrated circuits, Gordon Moore of the Intel Corporation developed what has become known as "Moore's Law": that technology complexity (minimum geometries and circuit density) doubles every 18 months, leading to a fourfold increase in circuit or transistor density every three years. The semiconductor community has summarized semiconductor technology requirements and developed the 15-year NTRS (National Technology Roadmap for Semiconductors) (SIA, 1994).1 These requirements, established by extending Moore's Law, involve scaling the minimum feature size by a factor of 0.7 every three years, from one product generation to the next. Table 4-1 shows industry's intent to continue increasing the number of available transistors on an IC while driving the cost per transistor down. Table 4-2 shows the plan for decreasing battery voltage while total IC power continues to increase because of the increasing operating frequency and the number of transistors on the IC. The reference to performance in Table 4-2 reflects the industry's desire to increase the operating frequency and number of circuit functions as transistor sizes decrease, which would lead to an increase in the total circuit power if adequate cooling methods can be used. Although the emphasis is on minimum feature size for the transistor as a function of time, the accompanying decreases in operating voltage and capacitance lead to an overall decrease in the power requirement for a specific circuit function while performance remains constant. More importantly, increased levels integration will support designs for the low power techniques mentioned earlier, such as increasing or repeating circuit functions for lower power 1 The NTRS is revised every three years, and a 1997 revision was in progress at the time of this report.
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Energy-Efficient Technologies for the Dismounted Soldier TABLE 4-1 Semiconductor Product Characteristics Year of First Shipment 1995 1998 2001 2004 2007 2010 Minimum Feature Size (µm) 0.35 0.25 0.18 0.13 0.10 0.07 Memory Bits/chip 0.017 0.007 0.003 0.001 0.005 0.0002 Cost/bit (millicents) 64 Mb 256 Mb 1 Gb 4 Gb 16 Gb 64 Gb Microprocessor logic (high volume) Transistors/cm2 4M 7M 13M 25M 50M 90M Memory cache (bits/cm2) 2M 6M 20M 50M 100M 300M Cost/transistor (millicents) 1 0.5 0.2 0.1 0.05 0.02 ASIC logic (low volume) Transistors/cm2 2M 4M 7M 12M 25M 40M Design cost/transistor (millicents) 0.3 0.1 0.05 0.03 0.02 0.01 Source: National Technology Roadmap for Semiconductors, 1994. architectures, adding chip memory to minimize circuit I/O, and selectively powering down circuits. The first NTRS was developed in 1992 and revised in 1994. A further revision is expected to be released in late 1997. The road map covers a 15-year time span (six generations of technology development) with minimum feature sizes decreasing according to Moore's Law. Although the road map focuses on the year products are first produced using a new technology, development is generally divided into four distinct phases: research, development, integration, and production. The research phase for a particular technology generation generally precedes production by three technology generations, or eight to ten years. The road map was created by an official Roadmap Coordinating Group with the support of eight technology working groups representing each critical technology for semiconductor product development and manufacturing: (1) design and test, (2) process integration, devices, and structures, (3) environment, safety, and health, (4) lithography, (5) interconnect, (6) materials and bulk processes, (7) assembly and packaging, and (8) factory integration. Related disciplines, such as metrology, modeling and simulation, electronic materials, standards, contamination-free manufacturing (CFM), and quality and reliability, were included as "cross-cutting technologies." Although the primary measures of progress have been decreases in minimum feature size and increases in transistor density, smaller feature sizes have led to related changes in fabrication technology, producing circuit operation at lower voltages and decreases in circuit capacitances, which have led to decreases in
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Energy-Efficient Technologies for the Dismounted Soldier TABLE 4-2 Semiconductor Product Technology Year of First Shipment 1995 1998 2001 2004 2007 2010 Minimum Feature Size (µm) 0.35 0.25 0.18 0.13 0.10 0.07 Power supply voltage (V) Nonportable 3.3 2.5 1.8 1.5 1.2 0.9 Portable (battery) 2.5 1.8–2.5 0.9–1.8 0.9 0.9 0.9 Performance Microprocessor circuits with cooling (W) 80 100 120 140 160 180 Logic circuits without cooling (W/cm2) 5 7 10 10 10 10 Maximum power (W) 2.5 2.5 3.0 3.5 4.0 4.5 Design and test Test cost/pin ($K) 3.3 1.7 1.3 0.7 0.5 0.4 Number of test vectors (M) 16–32 16–32 16–32 8–16 4–8 4 IC auto test capability (% BIST/DFTa) 25 40 50 70 90 90+ a built-in self-test/design for testability Source: National Technology Roadmap for Semiconductors, 1994. circuit power. In addition, increasing device densities have made possible dramatic increases in the complexity of circuits on a single chip (leading to "systems on a chip,") with an attendant decrease in power related to driving numerous off-chip capacitances associated with interfacing integrated circuits. Even with the primary emphasis of the NTRS on minimum feature size, the related reductions in power requirements for a fixed level of performance and the increasing levels of device integration would tend to reduce the power requirements of electronics for the dismounted soldier. Purpose The NTRS provides a high-quality database of industry goals, related needs to achieve the goals, and a framework that the semiconductor industry and government can use to focus R&D on the desired objectives. Although each critical technology area focuses on different needs, the integrated key elements of the road map are minimum feature size, memory density, logic transistors per cm2, and cost per bit or function (Table 4-1). Because of the industrial dominance of CMOS technology, CMOS has been used as the standard, and advances in other silicon technologies can be related to CMOS advances. Table 4-3 summarizes overall technology characteristics for an integrated chip and package. The complete road map addresses not only the chip design and fabrication technology, but also materials, including silicon and SOI, and related technology
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Energy-Efficient Technologies for the Dismounted Soldier issues, such as power and voltage trends, design and testing tools, and manufacturing defect densities. Although one objective of the NTRS is to foster and channel creativity in the R&D community, it was also intended to help suppliers anticipate the needs of semiconductor manufacturers. The road map also provides systems designers with a schedule for technology insertion in planning new products. The Army can use NTRS near-term projections to determine the availability of technology for implementing low power circuit designs in defense electronics systems. Challenges In addition to describing the industry plan for the availability of technology, the road map summarizes the developments in equipment and manufacturing technology necessary for staying on schedule. Many of these developments are identified as technology gaps that will require additional investment to support the road map. The most urgent "Grand Challenges" facing the semiconductor community in achieving smaller feature sizes and cost reductions (SIA, 1994) are described below. Improved Productivity The semiconductor industry has maintained growth by achieving a 30-percent-per-year per function cost reduction throughout its history. The increase in productivity has been achieved through innovations in design, reductions in device size, increases in wafer size, improved yield, and improved utilization of capital equipment. Increases in productivity have been offset by increased chip and technology complexity, chip sizes, and costs of wafer fabrication facilities. The cost of a new fabrication facility now approaches $2 billion. Some historical approaches to higher productivity, such as improving yield, are no longer valid (the yield of most processes is already high). Therefore, new ways must be found to increase productivity if industry is to continue the historical trend in cost (improvements in manufacturing technology are one possibility). Managing Complexity Sophisticated tools are required to deal with the exponential increases in the complexity of integrated circuits, including increasing numbers of masks and process steps, more layers of interconnect, special device structures, optical lithography that requires phase-shift masks and proximity correction for a variety of structures, and sophisticated planarization techniques. These new design tools must be able to cope with a factor-of-four increase in complexity with each technology generation, the use of mixed signal designs, and increases in power,
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Energy-Efficient Technologies for the Dismounted Soldier TABLE 4-3 Semiconductor Package Characteristics Year of First Shipment 1995 1998 2001 2004 2007 2010 Minimum Feature Size (µm) 0.35 0.25 0.18 0.13 0.10 0.07 Number of I/O connections (IC-to-pkg) 900 1350 2000 2600 3600 4800 IC frequency (MHz) Clock speed, high performance 300 450 600 800 1000 1100 IC-to-board speed, high performance 150 200 250 300 375 475 IC size (mm2) Memory 190 280 420 640 960 1400 Microprocessor 250 300 360 430 520 620 ASIC 450 660 750 900 1100 1400 Number of wiring levels (logic) 4–5 5 5–6 6 6–7 7–8 Source: National Technology Roadmap for Semiconductors, 1994. stress, and performance. In addition, new portable computing and signal processing requirements imply lower power systems emphasizing design goals other than improved performance. Advanced Technology In the past, large industrial organizations have invested heavily in advanced R&D, with or without government sponsorship. These investments have led to technological breakthroughs and leadership in the field by the United States. Although federal support is still available for advanced technology development in industry and universities, government investment has decreased dramatically in recent years. To ensure that low power technology for the soldier's electronics is available, DARPA should increase support for advanced technology, ranging from research on new electrical devices and circuits to improved manufacturing methods and the development of more efficient software design tools. In particular, large investments are required for facilities and apparatus, especially in the university environment. One challenge will be to distribute research facilities and programs to meet continuing technology requirements. Additional support is required for long-term research in areas such as nano-metrics metrology, nano-fabrication techniques, and new device structures. Fundamental changes are required in software development to produce high-quality software and in the optimization of cross-disciplinary technology, which requires expertise from a variety of engineering disciplines to provide
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Energy-Efficient Technologies for the Dismounted Soldier optimal solutions for specific problems (e.g., expertise in circuits, packaging, processes, software, and mechanical design to solve interconnect problems). Funding Although extensive resources are being invested in semiconductor technology, even greater resources are required for research in new technology to develop precompetitive technologies and to eliminate duplication of effort. The entire community, including the government, must support R&D on critical technology components with shared research funds. For example, technologies that are not commercially self-supporting, but are prerequisites for maintaining the technological leadership of the United States, include lithography tools, metrology tools, mask writers, masks, technology computer-aided-design (TCAD) tools, and inspection tools. The challenge is to implement an efficient funding strategy that covers all critical needs and to demonstrate new concepts prior to funding the development of full solutions. The published road map includes many other details. Because it represents the industry consensus, it is an excellent guide for the DoD regarding the planned availability of advanced technologies. For example, the road map includes plans for circuit complexity, power, and packaging specifications for future systems. In addition to technical plans, the road map provides guidelines for investments in technology and research to support the road map goals, and hence technology availability, for defense applications. One of the key technologies for investment is advanced lithography tools. Smaller devices enabled by advanced lithography will continue to reduce the power required for military integrated circuits. Military and Commercial Synergy The Army can take advantage of industry's commitment to staying on the road map by synchronizing its electronics technology cycles with those of industry. By migrating with the technology on a nominal three year cycle, the battery voltage for supporting industry requirements will decrease from 5.0 V in 1996 to 0.9 V in 2004, resulting in a factor of 30 power savings for a specific circuit function, from the voltage decrease alone. Even though the circuit voltage may plateau in the 0.9 V range, continued improvements in transistor density and performance through other technological advances are expected to support lower power integrated circuits. Although the industry commitment to remaining on the NTRS is strong, extensive resources must still be expended each year to advance the technology. Certain technology developments cannot be adequately funded through commercial sales. Because it could be detrimental to U.S. security for foreign countries to acquire a new technology before the United States and to ensure U.S. technological leadership, the entire community must support R&D on advances in
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Energy-Efficient Technologies for the Dismounted Soldier technology. The DoD can help maintain U.S. leadership by supporting the development of critical technology components needed by industry. Supporting technology advances will provide continued leverage for defense electronics, including low power electronics systems for the dismounted soldier. THEORETICAL LIMITS ON LOW POWER ELECTRONICS Because the NTRS predicts continued advances according to Moore's Law and does not address theoretical or practical technology limitations, the committee analyzed possible limits on continued advances. Appendix D focuses on the continued reduction in minimum circuit geometries leading to gigascale levels of integration (1 billion transistors per chip) (Meindl, 1995). Although the Army's low power systems may not require the maximum device density or the high performance that accompanies the decrease in design rules or minimum geometries, the lower voltages and capacitances supported by the decreasing device geometries and interconnects and the ability to tailor individual transistor drive currents are expected to yield reductions in both integrated circuit and system power requirements. Future opportunities for low power electronics or gigascale integration will be governed by a hierarchy of theoretical and practical limits. The five levels of this hierarchy are codified as fundamental, material, device, circuit, and system limits. At each level, there are two kinds of limits, theoretical and practical. Theoretical limits are determined by the laws of physics and by technological invention. Practical limits must, of course, be in compliance with physical limits but must also take into account manufacturing costs and markets. Because theoretical limits define the ultimate capabilities of electronics that could be provided to the dismounted soldier, the most important theoretical limits for low power electronics are discussed here. Broadly speaking, theoretical limits deal with the canonical operation of digital computing, the binary switching transition, and the interconnection of switching elements. The saturation level of gigascale integration does not approach the physical limits, and it will be possible to continue for at least another decade to reduce feature size and switching energy and increase the numbers of transistors per chip at the exponential rates of the past two decades. Beyond the next decade, however, a viable new suboptical microlithography technology will be required. For example, optical lithography will reach its practical limit at the 0.125 µm generation of chips (or shortly thereafter), and possible alternatives include extreme ultraviolet or soft x-ray lithography. The relatively short wavelengths of these alternatives will require new photon sources, new masking techniques, new resist materials and processes, and new metrologies. The challenges presented by these prospective advances appear to be disproportionately difficult compared to the challenges the semiconductor community has already met. Moreover, the same may be said about virtually all of the associated ultra clean (Ohme, 1994) sub-0.125 µm fabrication processes, such as ion implantation, rapid thermal
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Energy-Efficient Technologies for the Dismounted Soldier processing, and plasma enhanced chemical vapor deposition, that must accompany a suboptical lithography technology in a manufacturing environment. These difficulties can probably be overcome for two reasons. First, the principles of physics are not at all discouraging. Second, the economic incentives for succeeding are virtually irresistible. The prospects of scaling future species of metal-oxide semiconductor field effect transistor (MOSFETs) to 25 nm minimum feature sizes (and perhaps beyond) are promising. Furthermore, between the 25 nm MOSFET and the 0.118 nm tetrahedral radius of a silicon atom are two decades of opportunity to scale dimensions, about as much as has been achieved so far. Discounting any sub-25 nm breakthroughs, between the 125 nm and the 25 nm generations of chips, four or five intermediate generations can be forecast, which should make possible the trillion transistor chip (1 trillion devices), or terascale integration. Although the potential to scale to 25 nm and beyond exists, the challenge of inventing structures and manufacturing hundreds of billions of sub-50 micron transistors will require enormous research effort by both government and industry. Following the anticipated achievement of the 125 nm generation in about a decade, at a rate of three to six years per succeeding generation, scaling should be expected to continue into the 2020s. Unfortunately, however, engineering challenges associated with the scale reductions forecast by the NTRS and with designing the ultrascale ICs may not be overcome, because DoD has eliminated almost all funding for long-range research on the fabrication and design technologies necessary for continued exponential improvements. INDUSTRY CONSENSUS The NTRS outlines the industry consensus about technology directions and advances for silicon. In addition, numerous professional societies, universities, and government agencies have focused on advanced technology development, including the annual IEEE International Symposium on Low Power Electronics and Design and the special IEEE Transactions and Proceedings and the DARPA low power electronics program. Each of these focuses on power reduction for mobile microelectronics. Centers for Low Power Electronics Industry's recent focus on low power electronics has spurred academic research. Numerous universities have established low power research programs and, in many instances, special design centers to provide a forum for establishing research directions, discussing industrial needs, presenting early results, and solving specific design problems. Because of the pervasive need for low power electronics for portable systems, several commercial, professional, and university societies have focused
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Energy-Efficient Technologies for the Dismounted Soldier on low power technologies. For example, various academic centers for low power electronics are addressing fundamental, industry-relevant research problems in the design of ultra-low power portable computing and communications systems. These centers are sponsoring basic and applied research for the development of the next generation of mobile and portable ultra-low power electronic systems and are establishing mechanisms for timely technology transfer, including research results and the exchange of scientific personnel among universities and industry. Participating companies advise the academic centers on current and projected industry needs while monitoring and participating in research. International Symposium on Low Power Electronics and Design An annual IEEE-sponsored symposium provides a forum for the presentation of advances in low power systems and components. All aspects of designing a low power product, from fabrication technology and circuits to systems and software, are included. The symposium is the result of a merger of separate symposia on low power electronics and low power design and focuses on two topic areas: (1) systems and CAD and (2) circuits and technology. Papers report on significant advances in the field, present new ideas, and often include ways to use new concepts in hardware and practical applications. DARPA Low Power Electronics Program The stated goal of DARPA's program was to develop a mainstream technology base to enable a new class of electronic systems that dissipate less than 1 percent of the power of systems based on conventional technology. The program was divided into two sections: circuit architecture and power management; and, materials and device technology. The first area included the development of low power CAD tools, power conversion, recovery, and distribution. The second area started with a conventional 3.3-V bulk CMOS technology with migration to a 1.0-V SOI CMOS process. In both areas, the emphasis was on verification and integration with demonstration of a viable SOI design and manufacturing process in a low power, high-performance electronic system. Although many industry achievements are proprietary, the program demonstrated a capability of 0.9-V operation with power requirements of 0.01 mW/gate-MHz. The DARPA program successfully demonstrated significant reductions in power for a variety of applications and has provided enabling research funding to universities for low power research. Because of the importance of low power research to the Army, a follow-on program should be initiated.
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Energy-Efficient Technologies for the Dismounted Soldier FINDINGS Continued progress in silicon technology over time has led to dramatic decreases in device sizes, improvements in circuit performance, increases in the density and complexity of circuits on a single integrated circuit, and decreases in energy requirements per circuit function. The NTRS outlines industry's technology development plan. In response to market demands, the commercial sector continues to produce products with expanded capabilities to meet consumer demands. These advances can be leveraged if the Army can synchronize its upgrades with commercial advances. Keeping pace with industry would support the military policy of using more commercial-like products to control costs. With major technological advances being made approximately every three years in industry, substantial decreases in power are possible for specified functions, which can mean a longer mission time for a fixed energy source, a decrease in weight and volume if the source is scaled for the same mission time, or an increase in functionality for a fixed mission and source. In any case, significant advantages can be realized. Keeping pace with industry and upgrading technology every three years may require restructuring the Army's design and procurement process so that contractors automatically upgrade designs as improved technology becomes available. For example, a basic ASIC (application-specific integrated circuit) design could be implemented using a high level design language specification and the designs simply recompiled periodically with the latest technology. This concept could be enhanced by using modular designs. A policy could require limiting procurement for a specific technology lot and could require discarding older products. A ''throw away technology" approach would be similar to the present commercial practice of upgrading personal computers every few years. By correlating military procurements with commercial specifications, the Army could realize many of the volume cost advantages, as well as technology advantages, enjoyed by commercial consumers. To keep up with industry trends in reducing power for mobile functions, Army contractors will need to change their system, subsystem, and integrated circuit design methods. Instead of designing for the smallest chip area or the highest speed, they should design for minimum power requirements. This new approach would require the development of CAD tools (system architecture, circuit design, and layout) that minimize power and manufacturing costs and maximize reliability—design tools that are not available commercially. The NTRS defines critical technology areas and in some cases identifies research gaps that may prevent technology breakthroughs. Because the road map is upgraded regularly (every three years), the Army can provide input through DoD representation on the road map committee or through other government representatives, such as the National Institute of Standards and Technology or the national laboratories. The Army can use the road map to project the availability of technology in specifying new systems. Supplemental R&D support will be necessary for industry and universities in specific areas to maintain the road map
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Energy-Efficient Technologies for the Dismounted Soldier schedule. Because much advanced technology development in the past has been done at universities, the Army should continue to encourage funding from DoD to universities through the Army Research Office and DARPA. A number of special conferences, symposia, and focus centers have been created to encourage interest and advancements in technologies for low power electronics. Although Army and contractor personnel normally participate in many conferences, the Army could alert industry and university researchers to specific defense needs by formally joining several university focus centers and supporting projects that are aligned with Army needs. Participation in the specialty center activities and conferences is one way for the Army to obtain up-to-date information, to inform the centers and industry about military needs, and to provide the Army with information on available technologies, architectures, and designs. Software development should also focus on minimizing power requirements. Each instruction should be written or compiled to minimize power. Software implementation is related to logic design and physical circuit design. Although private industry may have software development tools that minimize power requirements, the Army may have to develop new tools to compile application software to minimize power for military applications. The general trend in mission planning has been to provide general-purpose capabilities for each soldier. The aim has been to maintain as much latitude as possible to support new mission requirements and also to capture cost savings by procuring standardized, interchangeable systems. Providing standard, general capabilities, however, requires a good deal of overhead that increases power requirements. The electronics systems that require low power performance should be tailored to meet specific soldier needs. Power overhead functions can be minimized by using dedicated circuit and subsystem hardware instead of general-purpose programmed hardware and circuits. Although general-purpose electronic circuits support product standardization and maximize the number of applications, they usually consume more system power than necessary. By designing custom circuits for dedicated functions, the total system power can be reduced.
Representative terms from entire chapter: