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1. What is the right mix of HDTV and SDTV as the digital service evolves over time? There are a variety of introduction scenarios for digital television, ranging from HDTV only, to SDTV only, to various mixes of the two. To preserve the HDTV broadcast option no matter how digital television service is introduced, SDTV receivers must be able to decode the HDTV signal. It is assumed here that SDTV receivers with such HDTV-decoding capability are both practical and cost effective. It is thus entirely practical to preclude SDTV-only receivers. Therefore, the introduction of SDTV would not prevent later introduction of HDTV because fully capable digital receivers would already be in use.

2. How quickly can National Television System Committee (NTSC) broadcasting be discontinued? The receiver design approach described herein can be applied to low-cost set-top boxes that permit NTSC receivers to be used to view digital television broadcasts. The existence of such decoders at low cost is implicit in any scenario that terminates NTSC broadcast.

Cost and Complexity of Full-Resolution HDTV Decoder Components

The single most expensive element of a video decoder is the picture storage memory. A fully compliant video decoder for U.S. HDTV will require a minimum of 9 MBytes of RAM for picture storage. An HDTV decoder will also require at least 1 MByte of RAM for channel buffer memory to provide temporary storage of the compressed bit stream. It can be expected that practical HDTV video decoders will employ 12 to 16 MBytes of specialty DRAM, which will probably cost at least $300 to $400 for the next few years and may be expected to cost more than $100 for the foreseeable future.

The IDCT section performs a large number of arithmetic computations at a high rate and represents a significant portion of the decoder chip area. The inverse quantizer (IQ) performs a smaller number of computations at a high rate, but it may also represent significant complexity.

The SP and VLD logic may also represent a significant portion of the decoder chip area. At the speeds and data rates specified for U.S. HDTV, multiple SP/VLD logic units operating in parallel may be required in a full HDTV decoder.

Cost Reductions of HDTV Decoder

This section describes several techniques that can be applied to reduce the cost of an HD-capable decoder. The following decoder subunits are considered: picture storage memory, pre-parser and channel buffer, SP and VLD, inverse quantizer and inverse discrete cosine transform, and motion compensated prediction. The discussion refers to Figure 1, which is a block diagram of a conventional SDTV decoder; and Figure 2, which is a block diagram of an HD-capable decoder. The blocks, which appear in Figure 2 but not in Figure 1, have been shaded to highlight the differences between an HD-capable decoder and a conventional SD decoder.

Picture-Storage Memory

As described in Ng (1993), the amount of picture-storage memory needed in a decoder can be reduced by downsampling (i.e., subsampling horizontally and vertically) each picture within the decoding loop. Note in Figure 2 that residual or intradata downsampling takes place after the IDCT block and prediction downsampling is done following half-pel interpolation blocks. The upsample operation shown in Figure 2 serves to restore the sampling lattice to its original scale, thus allowing the motion vectors to be applied at their original resolution. Although this view is functionally accurate, in actual hardware implementations the residual/intra downsampling operation would be merged with the IDCT operation, and the prediction downsample operation would be merged with the upsample and half-pel interpolation. In an efficient implementation the upsample—half-pel interpolation—downsample operation is implemented by appropriately weighting each of the reference samples extracted from the (reduced resolution) anchor frame buffers to form reduced resolution prediction references.

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