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3 Manufacturing of Computer Systems INTRODUCTION The manufacturing of computer systems includes a range of activities that translate a design into hardware and validate its per- forn~ance. The major manufacturing technology that makes state- of-the-art computer systems possible is semiconductor technology. Moving from chip design to chip fabrication requires sophisticated CAD tools, simulators, software to validate the design, and a sig- nificant amount of processing power. Once the chip is fabricated, testing it is a major requirement, first to locate any remaining design or processing errors, and later to characterize the individual chips. While the manufacture of semiconductors is the key to computer systems, other major technologies are also essential, inclucling the manufacture of peripherals (e.g., storage technology, both magnetic and optical) and packaging technology. The latter ranges from the packaging and testing of semiconductor (1evices (with pin counts exceeding 300 pins per package) to larger scale packaging issues where heat dissipation is a major problem. 64
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MANUFACTURING OF COMPUTER SYSTEMS IMP ORTANCE OF MANUFACTURING 65 When thinking about controlling exports of computer technol- ogy, policymakers need to distinguish between cases where the ability to replicate a product is important, necessitating manufacturing ca- pability, and cases where the existence of a single copy would mean- ingfully advance CMEA capabilities. For example, having a single supercomputer might be quite beneficial to some projects, but a sin- gle chip implemented in state-of-the-art technology would be of no value to a country that does not have the appropriate technology base to replicate it. The key to manufacturing state-of-the-art inte- ~rated circuits is having the appropriate manufacturing equipment (e.g., lithography) and the materials (e.g., bulk silicon, photoresist). The issue is whether any of this equipment should be controlled, and if so, how effectively it can be controlled. It should be noted that the United States has become dangerously dependent on Japan for much of the equipment used for semiconductor manufacture. This problem is now being redressed through the government-industry Sematech c, _ _ program. Semiconductor manufacturing equipment is complex arid the field is evolving rapidly. To compete economically with state-of-the- art integrated circuits, a manufacturer must continually upgrade his processing equipment. Another issue is whether this most advanced computer technology would be used to support military applications directly (e.g., guidance control for a smart weapon) or whether it would be used indirectly (e.g., to design military materiel). If the former, then having a manufacturing capability is more important to avoid another country's possible denial of components critical to the military system. Many military systems require components that are more robust than the readily available commercial components. For example, radiation-hard semiconductor components may be needed, and some systems must withstand induced electromagnetic pulse (EMP). But while the design rules or specific processing steps might change for these components, the basic manufacturing equipment remains the same as that used commercially. The lack of adequate manufacturing technology could affect de- velopment of a computer system in several ways: ~ The first is the inability to produce a working product at all. For example, lacking a critical processing technology, such as wafer steppers, could doom a project.
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66 GLOBAL TRENDS IN COMPUTER TECHNOLOGY The second is the inability to produce a product of sufficient quality. If the quality of a semiconductor product is Tow, whether due to design or manufacturing, the systems in which it is installed will be unreliable and costly to maintain. ~ The third is the inability to produce a product economically. For example, poor yield or lack of adequate automation might con- tribute to this problem. This would have a greater impact on com- petition in the marketplace than on meeting one's own high-priority needs. The fourth is the inability to produce in a timely manner. This could be caused by a lack of automation and hence insu~- cient volume; or a lack of key materials such as bulk silicon or photoresist; or a need to make too many iterations to complete the design-manufacturing cycle. The ability to manufacture one's own semiconductor products rather than relying on suppliers from another country is clearly preferable. But beyond relying on the end products (ICs or com- puters), there is also the question of being able to produce both the materials (e.g., bulk silicon) and the manufacturing equipment (e.g., wafer steppers) rather than relying on suppliers from other countries. SEMICONDUCTOR MANUFACTURE The United States has been experiencing about a 30 percent reduction every three years in the minimum linear feature size of devices on a chip. This reduction in feature size means that the same functionality can be placed in a smaller area (hence greater yield) and that chips can be made that have more devices. A feature size of 1.2 to 1.5 microns is widely practiced in industry, and some companies are starting to ramp up production at 1 micron. There is much development at submicron feature sizes, but no significant production of such components at this time. This 30 percent reduction every three years could continue for another two generations, resulting in feature sizes of 0.7 to 0.8 microns beginning to emerge around 1991 and feature sizes of 0.5 to 0.6 microns by 1994. As feature sizes decrease, the manufacturing equipment and pro- cesses must evolve with them. The costs of building semiconductor production facilities are also rising, with a full-scare factory now costing more than $100 million. The processes are also getting more complex, and it now takes more than 100 distinct processing steps to fabricate an integrated circuit. Ongoing research on new fabrication
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MANUFACTURING OF COMPUTER SYSTEMS 67 technologies is still a Tong way from production and use. Some of the techniques under development, such as direct-write lithography, may be useful only for limited volume production. The committee examined some of the global trends in semicon- ductor manufacture and looked at specific processing steps and their associated equipment. Major Technology Wends Wafer Size There is a trend toward larger wafer sizes, as seen in the demand for silicon ingots. The largest worldwide demand is for ingots to produce 4-inch wafers, with ingots for 6-inch wafers a close second. At present, there is a very small demand for 8-inch wafers, but it is expected to grow in the future. Any change in wafer size produces a ripple effect through the rest of the wafer fabrication industry to build equipment to handle the larger wafers. I'ower Temperature Processing Diffusion ovens operate between 950°C anct 1300°C. These high temperatures tend to warp the wafer and make alignment more difficult. Transistor drift may make it necessary to align the stepper _ %, _ ~ · ~ ~ · ~ · T · ~ ~ _ 1~ ~ _ _ _ 1 ~ ~ on a die- by-~le basis. lon lmplamallon may oe used lI1 p1~ O1 diffusion ovens for some steps, but not for all. Other changesinclude: ~ Plasma-enhance(1 chemical vapor deposition operated from 300°C to 650°C can be used to deposit silicon nitride en cl polysilicon. High-pressure oxide diffusion (10 to 50 atmospheres) operat- ing at 600°C to 700°C can be used to grow silicon dioxide films. ~ Rapid thermal processing operated at 700°C can be used to repair damage to the crystal lattice and anneal silicide or polysilicon. . Planarization Planarization is needed to put down multiple layers of metal. As feature sizes decrease and chips become limited by the metal interconnects, there is likely to be a demand! for additional layers of metal beyond the two layers generally available today. The problem wit! be to avoid seams and voids, and this is done with a combination of deposition, etching, and selection of materials.
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68 Automation GL OBA L TRENDS IN COMP UTER TECHNOL O G Y Automation is used increasingly in nearly all aspects of semicon- ductor processing. This is driven by several different needs. One is to get people out of sensitive manufacturing areas to avoid particle contamination. A second is to improve throughput. A third is to control complex processes, such as crystal growth. A fourth is to control complex equipment, such as ion implanters, and a fifth is to support testing of more complex devices. Wafer Fabrication Equipment This equipment is still produced primarily by the United States, which accounted for 59 percent of the worldwide market in 1987 (the declining value of the dollar has helped U.S. producers). However, there has been a 16 percent decrease in the U.S. position since 1979. To(lay some of the most sophisticated equipment, such as wafer steppers, comes from Japan. In 1986 Japan accounted for 34 percent of the wafer fabrication equipment market, and Europe accounted for 10 percent. The semiconductor market is cyclical, and those companies that depend primarily on wafer fabrication equipment for their business can be severely hurt by these cycles, as was GCA (United States) in 1986. The larger, vertically integrated companies can withstand these cycles better and generally attain a stronger market position in the Tong run. WAFER FABRICATION EQUIPMENT This section discusses the wafer fabrication equipment used in fabricating silicon-integrated circuits.) The committee has not at- tempted to deal with manufacturing for other technologies, such as gallium arsenide or mercury cadmium telluride. Much of the pro- cessing equipment is the same as for silicon. The wafer fabrication equipment market constitutes roughly 50 percent of the total equipment market for all semiconductor manufac- turing. The continued decrease in feature size places severe demands on the processing equipment. New technologies, such as e-beam lithography, deep ultraviolet proximity, and x-ray lithography, have 1 Information in this section was derived in part from VLSI Research Inc., The VLSI Manufacturing Outlook, 1986.
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MANUFACTURING OF COMPUTER SYSTEMS 69 been demonstrated in the laboratory but are still too complicated or too costly to be used in production lines at this time. Nevertheless, they represent advances so important that the transfer of even one piece of equipment incorporating them could be of significant benefit to CMEA, especially in military applications. , ~ Major Technology Mends and Leading Industry Players Mask Generation Masks and reticles are used to pattern the layers of material that make up semiconductor products. Most masks are made using e-beam machines, and this technology is not likely to change in the near future. Defect densities need to be Towered as feature sizes decrease. Perkin Elmer (United States) is a major supplier of e- beam machines. While the Japanese do not appear to be targeting this market for their machines, some U.S. companies do have their masks made in Japan. Microlithography This is the process of creating the successive patterns of mate- rial, properly aligning each layer on the preceding layers. Optical alignment is the dominant technology, and it is likely to remain so for some time. The wafer stepper is the major equipment now used for wafer exposure. The Japanese have been extremely successful in penetrating this market, and they now account for nearly 50 per- cent of worldwide sales. The four major suppliers are Perkin-Elmer (United States), GCA (United States), Canon (Japan), and Nikon (Japan). X-ray lithography accounts for only a very small percentage of total sales, but as feature sizes decrease, sales are expected to increase. Steppers expose a die or set of dice at once and are wed suited for large-volume production. A technique known as direct write uses an extremely fine beam of ions, electrons, or laser light to straw the features on the photoresist without the use of a mask. This technique is much slower than using a stepper, but it is cost-effective for smaH-volume production of specialized chips. Some techniques still in the laboratory, such as laser pantography, are able to both deposit and remove different kiwis of material that form a die. It is too early to tell how effective these techniques will be.
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70 Resist Technology GL OBA L TRENDS IN COMP UTER TE CHNOL O G Y A resist is a photosensitive material that permits removal of pat- terns of material selectively from the wafer. Kociak (United States) has been a major supplier of resists, but the United States seems to be lagging in the development of new resist technology. There appears to be a gradual and subtle shift to Japanese companies, such as Tokyo Ohka. A variety of equipment is used to clean the wafer, spin the resist on the wafer, bake the resist, and transport the wafers through the process. Some processes use a multilayer resist to improve planarization for VEST applications, but it is costly. There is experimentation with inorganic resists such as a combination of germanium and selenium. In 1986 U.S. manufacturers held slightly less than 50 percent of the market, down from nearly 80 percent in 1981. Major suppliers are Sil- icon Valley Group (United States), MT] (United States), Dainippon Screen (Japan), and TEL (Japan). Metrology Very precise measurements need to be made while processing the different layers of a wafer. Scanning electron microscopes (SEM) are used for these measurements. Major suppliers include Hitachi (Japan) and JEOf (Japan). Diffusion and Oxidation Diffusion equipment introduces impurities into the wafer to change the conductivity of the semiconductor. Diffusion equipment is one of the most refined and mature segments of capital equipment used in semiconductor processing. The diffusion equipment market (e.g., diffusion furnaces, high-pressure oxidation, and rapid thermal processing) accounted for about 7 percent of the total wafer fabri- cation market in the mid-l9SOs (about $200 minion annually). The key players are Tokyo Electron Ltd. (Japan), Bruce Systems (United States), and Thermco (United States). The United States controls about 55 percent of this market, with Japan a strong second. Ton Implantation Ion implanters directly inject dopant atoms (usually boron and
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MANUFACTURING OF COMPUTER SYSTEMS 71 arsenic) into semiconductor wafers. Ton-implant equipment repre- sents about 11 percent of the total wafer processing equipment mar- ket in the mid-1980s (about $340 million annually). Three different classes of machines exist for light doping (Iow to medium current), heavy doping (high current), and deep-level doping (high-energy atoms). Compared with the diffusion process, ion implanters have not yet been able to achieve the required depth of penetration nor the required surface concentrations, at least within reasonable times. The equipment is also very complex and subject to poor uptime. The major suppliers of ion implanters are Eaton Corporation (United States), Varian (United States), and Tokyo Electron Ltcl. (Japan). Etching and Cleaning Etching en cl cleaning equipment is used to selectively etch a film of material (e.g., silicon nitride, polysilicon, silicon dioxide, and aluminum) from a wafer, and to strip a layer of material (e.g., pho- toresist) from a wafer. There are two basic kinds of etching: wet processing, in which an acid dissolves a particular material, and dry processing, in which a plasma, ion, or ultraviolet source is used to re- move a layer of material. Etching and cleaning equipment accounted for 17 percent of the wafer processing equipment market in the micl- 1980s (about $500 million annually). Over the past decade there has been a trend toward dry processing, and it now accounts for 75 percent of the etching market. The United States controls about 70 percent of this market, and Japan about 26 percent. Leading sup- pliers are Applied Materials, Lam Research, and Tegat Corporation (all in the United States). Deposition During wafer processing, thin layers of conducting or insulating material must be deposited onto the wafer. There are three main de- position processes: chemical vapor deposition (CVD), used primarily to deposit nonmetallic films; physical vapor deposition (PVD), used mostly for depositing metallic films; and epitaxy, used for growing single-crystal silicon above the wafer surface. Of the several tech- nical approaches within each process, low-pressure CVD, sputtering POD, and molecular beam epitaxy are now the dominant thrusts. Deposition technology accounted for about 21 percent of the total wafer processing equipment market in the micI-1980s (about $660
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72 GL OBA L TRENDS IN COMP UTER TE CHNOL O G Y million annually). The United States accounts for about 52 per- cent of the worldwide market, Japan about 26 percent, and Europe about 20 percent. The leading suppliers of deposition equipment are Advanced Semiconductor Materials (Europe) for CVD equipment, Varian (United States) for PVD equipment, and Applied Materials (United States) for epitaxy equipment. Testing As feature sizes decrease, speeds increase, circuits get more com- plex, and pin counts increase, testing becomes a major problem. Current suppliers of testing equipment include Teradyne, Century, Megatest, and TriDium (all in the United States), and Take da and Richo (in Japan). ELECTRONIC CAD Computer-aidect design tools enable us to take advantage of the wafer fabrication equipment discussed in the preceding section. The complexity of modern circuits is so great that today's semiconductor products would not exist without them. The design time and cost would be prohibitive, not to mention problems of accuracy of design. Major Technology Trends There are two general trends in CAD software: toward smaller, less expensive platforms for running CAD programs, and toward more powerful CAD programs. These trends can be seen in the four generations of electronic CAD (ECAD) products, which are either on the market or soon to become available. The oldest generation consists of systems from companies like Calma, Applicon, and Computervision. They developed systems in the 1970s that now run on outdated custom hardware costing hundreds of thousands of dollars per workstation. They provide only basic graphic editing, and are essentially nothing but automated drafting tools. These systems are still used by some organizations. However, they are rapidly being replaced by products from other companies, mostly new startups. These companies themselves were unable to meet challenges of new startups, and are being driven out of the marketplace. The second generation consists of workstations marketed by com- panies like Mentor, Daisy, and Valid. All three of these companies
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MA N UFA C T UR ING OF C O MP UTER S YS TEMS 73 formed in the early l980s; of them, Mentor is by far the most suc- cessful. Mentor developed their software to run on commercial work- stations; both Daisy and Valid developed custom hardware as part of their systems, although they have since ported their software to commercially available workstations. These systems still provide lit- tle besides schematic entry and simulation for printed circuit boards and gate arrays. Attempts to integrate additional functionality, such as full custom IC layout, have not been successful. The big ad- vantage of the seconcI-generation systems is that they run on more modern hardware, with faster CPUs, more memory, and better user interfaces. Second-generation systems are now used widely in the industry. The third generation of ECAD systems is exemplified by the product offerings of Cadence (a merger of SDA and ECAD), SCS, and others. These systems attempt to provide support for design at both the schematic level (as in second-generation systems) and at the layout level. The systems tend to focus on frameworks for design, so that new tools can be integrated easily into the systems, and on place-and-route, which simplifies one of the most tedious aspects of custom IC layout. These systems are not as widely used as first- and second-generation systems, but they appear to be gaining acceptance. The fourth generation consists of younger companies such as Synopsis, Trimeter, and EDA. The goal of these companies is to automate many of the pieces of custom design with module generators and other synthesis tools. Products from these companies are either still under development or not yet widely accepted. Generally, hardware costs for ECAD systems are dropping as commercial workstations are used. At the lowest end are PC-based CAD systems. As more powerful microprocessors such as the Tnte! 80386 are used in PCs, they are approaching the computing power of low-end workstations. The total system cost for PC-based ECAD systems is only a few thousand doBars, versus the more powerful fuD- color workstations that can cost $50,000 to $100,000. Companies such as View Logic offer PC-based systems, and Daisy offers a Tower performance version of their product that runs on a PC. A somewhat orthogonal trend in addition to the two mentioned above is the appearance over the past five years of a number of ASTC houses, such as LSI Logic. These companies accept schematics and produce application-specific integrated circuits usually using gate- array technology. Internally, these companies have substantial CAD
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74 GL OBA L TR ENDS IN COMP UTER TE CHNOL O G Y expertise, but they do not export their CAD tools (this has an advan- tage for protectability). The performance levels that can be achieved with ASICs have improved dramatically over the past few years to the point where they rival the best hand-designed custom chips. The battles to produce the fastest S PARC chips are an example; it is quite possible that the ASIC houses will produce faster chips sooner than the fur-custom houses. Previously, full-custom design was almost always necessary to achieve high performance and reasonable density, but newer ASTC circuits are challenging this theory. It seems possible that within five years, custom layout wiD be used only for memory chips, with all other components, including all microprocessors, fabricated using ASTC approaches. If this occurs, it will vastly reduce the development time for the most complex and powerful processors, since the layout for ASICs is automated and can be completed much more quickly than for full-custom designs. A change to predominant use of ASICs would also change the structure of the CAD industry. End-users would use only schematic entry and simulation tools. Layout tools would be used only in a few ASIC houses; there would not be broad markets for them, and layout expertise would be concentrated in the ASIC houses. This has the benefits of making CAD expertise less available to the Soviets; but it has the disadvantage that, if the Japanese come to dominate the market, the United States could lose all layout expertise. Leading Industry Players As with other software, the United States dominates here. Vir- tuaBy all the new developments in CAD come from the United States and all the major corporate players are American. The en- trepreneurial environment of the United States has resulted in dozens of CAD startups over the past 10 years, whereas abroad CAD is car- ried out primarily in large centralized organizations. Of the various startups, Mentor, Cadence, and Synopsis either have strong market positions or products that show great potential. Major U.S. manufacturers of semiconductor products are developing ECAD tools for internal use and will not make these tools commer- ciaby available. The Japanese appear to have excellent ECAD tools, with func- tionaTity equivalent to large U.S. corporations, such as IBM and AT&T. However, the tools exist only in large companies, such as
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MANUFACTURING OF COMPUTER SYSTEMS 75 Hitachi and NEC, and tend to be for internal use only. Their soft- ware is also based on large mainframes, rather than on more modern workstations as in the United States. Many U.S. companies are successfully selling CAD software in Japan because the Japanese companies do not tend to make their software available to others. Europe does not have much to speak of in ECAD software. Sev- eral of the large companies (e.g., Siemens) have internal development organizations, but they are not a threat in the market. Other Asian companies apparently have some interest in CAD software. For example, SDA has a development organization in Tai- wan. Some CAD projects are under way in both India and Israel, although they are not very influential right now. MASS STORAGE Major Technology Trends The major components that must be manufactured in a disk are the read/write heads, the recording media, and the mechanical moving parts. The current trend is toward thin-fiIm heads, and the manufacturing techniques are similar to those used in semiconductor manufacture. Sputtering techniques are increasingly being used in the manufacture of the recording media, and these are also derived from similar systems user! in semiconductor manufacture. Thus, there is considerable commonality in the manufacture of disks and semiconductor devices. Rigid disks typically use an aluminum manganese substrate, while tapes and flexible disks use a polymer substrate. Most of the small capacity disk systems currently use iron oxide as the magnetic material, but for systems capable of storing more than 60 Mbytes, there has been a move to thin films of metallic alloys containing mainly nickel and cobalt. Most thin films are deposited on the disk substrate using a plating process where the disk is immersed in a chemical bath. Thin films can also be deposited using a sputtering process similar to that used in semiconductor manufacture. Sputter- ing is currently more expensive, but it is easier to add trace elements such as chromium or rhenium to improve its coercivity, that is, the materiaT's resistance to reversal of its magnetization. About 20 per- cent of ah the disk-recording media are now produced by sputtering, including the recording media for all magneto-optic systems. One company, Komag, produces recording media only by sputtering.
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76 GL OBA L TRENDS IN COMP UTER TECHNOL O G Y Inductive and magnetoresistive thin-fiIm heads are now replac- ing ferrite heads. Thin-fiIm heads are manufactured using techniques borrowed from the manufacture of semiconductor devices. Magne- toresistive heads are used for reading only, but offer at least an order of magnitude more sensitivity than inductive heads. State-of-the-art systems use both kinds of heads in a single system. Because of the small size of the magnetoresistive heads (0.03 to 0.05 microns), they can be inserted in the gap of an inductive head. Integrating a mag- netoresistive head with an inductive head is possible with current manufacturing technology, and it significantly improves the perfor- mance of the system. Magneto-optics uses a laser to raise the temperature of a mag- netic material whose coercivity drops with increasing temperature (around 150° C). Reading uses the same laser but at Tower power and with the beam polarized. The light undergoes a rotation of the plane of polarization when the polarized light is reflected off a magnetic medium. Depending on whether the rotation is clockwise or coun- terclockwise, the bit is a zero or a one. Magneto-optic systems have just begun to reach the market. Both Sony and Sharp have started to market products in the United States. Each offers a 600-Mbyte system with a 5-1/4-inch disk having about a 100-miBisecond access time and a 1-Mbyte transfer rate. The current price is about $5,000, but it should drop within a couple of years to less than $1,000. A major difference in manufacturing a magneto-optic system compared to a conventional magnetic disk system is in the read/write head. This is because of the use of optics to focus the laser. The major components for the heads are the diode lasers and the optics, both of which come primarily from Japan. The Japanese assembly techniques are sufficiently advanced that the final alignments can be made without employing a rotating disk surface. In the United States, final alignments are still done using a rotating disk surface. The recording surfaces for the magneto-optic systems have small grooved tracks 0.07 microns deep, 0.7 microns wide, and spaced about 1.6 microns apart. The plastic substrates for the recording media can be produced using a stamping process, with the master being created using photolithography techniques, or by using injection molding techniques. Sputtering equipment is used to deposit a magnetic surface about 0.1 micron thick on the substrate. This equipment is similar to that used in the semiconductor industry, where the major producers are Varian (United States), UIvac (Japan), and Leybold (West Germany).
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MANUFACTURING OF COMPUTER SYSTEMS 77 Transfer rates can be significantly increased by using multiple read/write heads, and access times can be significantly improved, but they represent major engineering challenges. One of the most inter- esting technology challenges will be to make a read/write head that integrates the laser and the optics on a gaDium-arsenide substrate. This would make possible a magneto-optic system with multiple- recording surfaces as in the IBM 3380. Multiple-recording systems are also possible with less advanced technologies. The companies that are currently developing (or have developed) magneto-optic systems incliu(le Sony, Sharp, and Hitachi (Japan), and Verbatim and Maxtor (United States). All the read/write heads are likely to come from Japan, with the optics being produced by Olympus and MinoTta and the diode lasers by Hitachi and Mat- sushita. PACKAGING TECHNOLOGY Major Technology Mends Rapid developments in device technology will call for dramatic changes in packaging technology.2 Production feature sizes are at 1 micron (HP is reported to be using 0.6-micron CMOS in its HP- 2SC calculator). The number of circuits is likely to increase four times every three years, gate density to increase two and a half times every three years, and chip size to increase one and a half times every three years. Given these projections, device packages must become larger on the order of one and a half times every three years. In addition, increases in memory chip size will require an increase in the memory package size and density, and memory density must increase on the order of four times every three years. Given the limitations of packaging technology, the most compet- itive technologies are flip chip and tape-automated bonding (TAB). For the high-lead count (400-600) interconnect, the most popular choice for the 1990s is flip chip, with TAB as an emerging pos- sibility. Conventional TAB technology (i.e., thermal compression bonding with bond pads on the periphery of the chip) is limited by future requirements for higher interconnect density (adjacent spacing problem too small for conventional soldering). TAB can be aided 2Based on interviews with Japanese companies.
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78 GL OBAL TRENDS IN COMP UTER TECHNOL O G Y by new bonding techniques (e.g., laser bonding). Flip chip technol- ogy would be more desirable for future packaging needs, given no other alternatives. Early in 198S, with these limitations in mind, one Japanese company started a pseudo chip-on-wafer development project where silicon is used as the substrate. The driving force in the development of packaging technology in Japan has been the competition in the consumer electronic products sector (see Appendix E). One of the major trade-offs is the physical trade-o~ between density and cost. Future developments in packag- ing technology will require new materials to reduce costs and improve interconnect densities. Many Japanese companies are expanding the use of ceramic substrates and developing glass epoxy substrates. Use of copper polyimide substrates is also increasing in Japan (e.g., NEC uses copper polyimide for the interconnect layer in the SX-2~. In the area of computer performance for top-end systems, maxi- mum gate density is critical if a computer with a 1-nanosecond (us) cycle time is to be achieved in the next 10 years (supercomputers today have cycle times of 4 to 6 us). While Fujitsu and Hitachi are basing advances in gate density on state-of-the-art printed circuit board technology, NEC has focused on replacements for the current printed circuit board technology in its SX series. NEC will be able to advance to higher performance systems using an extension of its current technology. NEC uses a multilayer ceramic package that fea- tures a "flipped TAB carrier" where chips are mounted with TAB on a ceramic cofired substrate with copper-polyimide interconnect on top. This approach is extendable to higher gate densities. Implications of Future Technologies Because of power dissipation requirements, cooling technology will dominate the packaging design considerations for emitter cou- pled logic (ECL) technology, as the water-cooled systems of IBM, NEC, and Sperry illustrate. CMOS power dissipation is so Tow that we can expect even some high-performance systems to be air cooled in the intermediate future. The situation may change because of the increased power dissipation at higher frequencies that is charac- teristic of CMOS devices. Given the above, from a packaging and interconnect perspective, the speed goals for high-performance pack- ages will be determined more by the drivers and the interconnects than by the speed of the switches. Demands for increased functionality wiD mean greatly increased
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MANUFACTURING OF COMPUTER SYSTEMS 1 ,000 CD ._ o TO 100 a) Q z 100 79 - Random Logic / , , / Microprocessors - SRAMS - DRAMS / , ~ - ~ ,, Micros ,, / ~ 1 / ~ Random Logic ~ , Do/ - r RAMS l l 1 0 1 4 16 64 Memory (kbytes) Microprocessors I ~ 4 8 16 32 64 256 1 024 1 ,000 1 0,000 1 00,000 Random Logic (gates) FIGURE 3.1 Digital pinout increase with IC complexity. SOURCE: Courtesy of BRA Management Technology, Ltd. density of gates for VEST ICs. As this complexity increases, the number of pins can be expected to increase dramatically. The impli- cations from a packaging perspective are that the dual-inTine-package (DIP) and its variants will not be able to satisfy the thermal, power, pitch, number of leads, and other demands of VESI. Packages with numbers of pins in excess of 100, which represent today's micropro- cessors, are barely handled by DIP packages. As logic applications increase, higher pin counts will be necessary, in excess of 500 T/Os, which in turn will mean smaller feature sizes at the substrate level (see Figures 3.1 and 3.2~.
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80 10 o ~~ 8 ._ E - a rat ._ An a) 4 ~5 A_ a) GLOBAL TRENDS IN COMPUTER TECHNOLOGY \ 2 . O ~ _ l 1965 '70 '75 '80 '85 90 25 in 20 ._ a' N ._ en a' <~ 1 0 a) 11 FIGURE 3.2 Feature size trends. SOURCE: Courtesy of BRA Management Technology, Ltd. 5 O I I _ 1965 '70 '75 '80 '85 '90 \ - - ~ l I As the feature sizes shrink, first- and second-level interconnect geometries wiD also need to shrink. Consequently, printed circuit boards will not be able to meet the requirements, particularly that for Tow cost. A case in point is Fujitsu's 42-layer PCB used in its M780 supercomputer, which has an aspect ratio of 20:1. Figure 3.3 compares substrate cost to total useful signal area, and indicates where future packaging technologies are likely to go. Packaging Issues Packages will have to be built from materials with high thermal coefficients of expansion, a wide range of dielectric constants, flexion, and Tow manufacturing cost. Likely candidate materials are ceramics, glass-epoxies, and insulating polymers (primarily copper polLyimide). Reliability and quality assurance requirements are becoming more demanding, as the cost of repair and rework (particularly in the field) increases. At the same time, however, testing of both chips and circuit boards is becoming more difficult and costly as complexity increases. As interconnect becomes more complex, an in- creasingly difficult problem is posed by the requirement to determine which parts are functional before chips or packages are committed to boards or substrates. At the same time, means for testing that do not contaminate or otherwise damage the substrate, wafer, or board will need to be developed as densities get greater and sizes smaller. Conventional probe testers will probably not suffice to test either
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MANUFACTURING OF COMPUTER SYSTEMS 1 0000 _ 1 000 s . _ - C) CD 8 100 _ a) Q cn 1n 68 PIN Dl l I l (~/: _ ~ I ~ 1 /111 111 1 68 PIN 68 PIN CC TAB 1 1 1 1 1 1 j 1~: _ _ (_16L) I ~ H3SL ~ I 100 200 300 NOTE: PCBs SS Single Sided DSPTH Double Sided 4L Four Layer 8L Eight Layer HYBRIDs H3SL 3 Signal Layer FIGURE 3.3 Substrate cost versus signal area. SOURCE: Courtesy of BRA Management Technology, Ltd. 81 I Emerging Technologies I in Chip Carriers I and Substrates LSI VLSI t l l l 1 400 500 5000 10000 Density (inches/inch2 (useful total signal area)) NOTE: TYPICAL DENSITIES FOR DIFFERENT IC PACKAGES Type | STAB (20 mil) I Pads 68 156 68 156 68 In/ln2 347 339 139 160 44 CC (50 mil) DIP (100 mil) The figures in the table above for in/in2 are for an area that includes the space taken by the packaged IC. unpassivated substrates or active ICs, in terms of size and damage. Consequently, new testing approaches will emerge in the near term, and these will be critical to the manufacturing process. Two ap- proaches seem viable nondestructive testing of both substrates and active chips, or self-testing chips. For high-lead count devices, TAB wiB continue to have significant technical and cost advantages, particularly if the TAB system is mated to an on-tape testing and burn-in system. It is not possible at present to perform this testing while the chips are still in wafer form because of the difficulty in making good nondestructive electrical contacts directly to the chip bonding pads. On-tape testing permits more favorable probe geometries as well as mass testing. TAB also produces mechanically stronger bonds, higher resonant frequencies, and Tower lead impedance. The mechanically compliant nature of TAB also presents the possibility of mounting very large chips directly
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82 GL OBA L TRENDS IN COMP UTER TE CHNOL O G Y to substrates without concern for fatigue cracking of the outer lead bonds (cracking is a deficiency of present solder bump attachments). At present, much of the TAB equipment is designed around low-lead count devices (up to 64 I/Os). To accommodate the high-lead count requirement, improvements in both equipment and beam lead tape are needed. Leading Industry Players The principal players in the packaging and interconnect areas vary by technology. For TAB they include IBM, several large verti- cally integrated Japanese companies (see Appendix F), Honeywell- Bull in France, Siemens AG of the Federal Republic of Germany, en c! a consortium of companies supported by the EEC's ESPRIT program. Ceramic package technology is dominated by Japanese companies, especially Kyocera, in leading-edge applications. BuD has developed a unique process for one type of TAB technology (burn-in chip-on-tape) at its plant in Angers, France. It is consid- ered the world's expert on this one process, and the company has developed some unique equipment. Siemens has developed a high-pin-count, high-performance TAB package called Mikropack. Siemens will use advanced TAB tech- nology for a new high-end computer. The TAB bonding equipment has been developed jointly with Farco and is not generally available except through Farco. The largest chips used in the computer are 12 mm square, have 340 I/Os (with 256 signal pads), and dissipate up to 20 to 25 W. The chips are directly flip-TAB mounted on the boards and are not hermetically sealed. CONCLUSIONS Because of their role as enabling technologies, high-end manu- facturing technologies are especially important to control. State-of-the-art manufacturing equipment and electronic com- puter-aided design systems are the key to manufacturing state-of- the-art integrated circuits. Major changes in IC technology cause changes to cascade throughout the manufacturing process. The United States is increasingly dependent on Japan for semi- conductor manufacturing equipment. Both Japanese and West Eu- ropean countries are leaders in certain aspects of packaging.
Representative terms from entire chapter: