Semiconductor Consortia in Japan: Experiences and Lessons for the Future
Tokyo Institute of Technology and Hitotsubashi University
AN ARMADA OF PROJECTS
When the Japanese semiconductor industry suffered a slump in the 1990s, policymakers looked to the past for ideas about how to revive it. Having been very pleased with the results of the Very Large-Scale Integrated Circuit (VLSI) project in facilitating the rise of Japanese semiconductor industries in the 1980s (Morris 1990), Japan launched an armada of projects that mirrored this strategy, including the Semiconductor Leading Edge Technologies, Inc. (Selete),1 Association of Super-Advanced Electronics Technologies (ASET),2 Semiconductor Technology Academic Research Center (STARC),3 Millennium Research for Advanced Information Technology (MIRAI),4 Highly Agile Line Concept Advancement (HALCA),5 Advanced SoC Platform Corporation (ASPLA)6 (ERI-JSPMI 2002), Extreme Ultraviolet Lithography System Development Association (EUVA),7
System in Package Consortium (SiP),8 Consortium for Advanced Semiconductor Materials and Related Technologies (CASMAT),9 Low Energy Electron Beam Proximity Projection Technology Consortium (LEEPL),10 VLSI Design Education Center (VDEC),11 and New Intelligence for IC Differentiation (DIIN).12 Among the consortia, VDEC at the University of Tokyo and DIIN at Tohuku University, both initiated by the Ministry of Education, Culture, Sports, Science, and Technology, have somewhat different founding purposes than other industry-centric consortia.
Some of the cooperative development projects of the industry-centric consortia have already been completed, including. Phase 1 and 2 of the ASET project and the HALCA project. Semiconductor technology development of Phase 1 of the ASET project was completed four years ago with the goal of “the development of photolithographic elemental technologies for 130nm-70nm and beyond and the development of basic elemental technologies of semiconductor processes.” It is now time to review the results.
In Phase 1 of the ASET project, a series of experiments called “Super Advanced Technology” were carried out as contracted research. A total of eight semiconductor-related projects were implemented as the part of the series. There were three electron beam (EB) related projects: One was the “development of high speed EB direct writing equipment.” Two were X-ray lithography-related projects, one of which was the “development of proximity X-ray lithography.” Three other projects were the “development of ArF lithography,” “plasma physics and diagnostics,” and “development of surface cleaning and simulation.”
These projects yielded impressive results, including 1,288 technical disclosures, 246 patent applications, and 101 registered patents. As an example of the content, the in “plasma physics and diagnostics” produced basic technology development in correlating process evaluation indicators such as selectivity and process distribution to equipment parameters such as process pressure and plasma electron density.
Though the results of the research were satisfactory, the projects received little appreciation. Why did Phase 1 of the ASET project, intended to be the second Ultra LSI Lab, fail to achieve a similar level of appreciation? Based on the following circumstances, we will see the expected role and behavior of consortia.
BACKGROUND CIRCUMSTANCES OF CONSORTIA ESTABLISHMENT
The research and development (R&D) targets of the existing consortia can be classified into three categories: investigation of individual process technology
LEEPLE’s homepage has already closed.
and material (MIRAI, EUVA, SiP, CASMAT and LEEPLE); development of semiconductor devices (MIRAI, Selete, and ASPLA); and development of device design support technologies (STARC). All of these activities are, in a sense, efforts to improve the efficiency of R&D performed by distinct organizations within major IDMs. Such work may be the development of elemental technologies and material technology by a research group, the development of devices by a device development group through the integration of elemental technologies, and the efficiency improvement of the design by a design technology development group within a firm.
The most significant change that current consortia such as Phase 1 of ASET or Selete before it became ASUKA have experienced is that of the member constituency. Though most of the results of Phase 1 of the ASET project were assumed to be fed back to the improvement of semiconductor manufacturing equipment, the equipment manufacturers were not directly involved in the promotion of research work. Based on the perception that such organization hampered the implementation of the project results, current projects such as EUVA, SiP, CASMAT, and LEEPLE (but not MIRAI) that affect process technologies and materials are organized by equipment and material manufacturers as well as device manufacturers. Among them, SiP and CASMAT are organized only by equipment and material manufacturers.
Three consortia that address device development (MIRAI, Selete, ASPLA) aimed to reduce R&D costs by sharing the development cost that had increased with technological advancement. The consortia also aimed at offsetting the reduction in R&D personnel within IDMs that had started in the late 1990s. These requirements have been the consistent missions of the consortium related to the Japanese semiconductor since the establishment of ASET and Selete of 1996 as can be seen in the following statement on ASPLA’s homepage.
To maintain the competitiveness of Japanese semiconductor companies in the world market, it is necessary to improve the development efficiency by sharing the huge development cost among the members and by standardizing the technical area where sharing was possible in the SoC design and process and to concentrate the resources on the forte. This achieves the effective use of the resource, the reduction of development time and cost, and the diversification of the design property and the process that can be mutually used. In addition to this, the optimum technology transfer to the member companies becomes possible by finishing up the result of development in the platform as an organized technology. Moreover, it is expected that the technologies become de facto standard in the world by globalizing the access to the ASPLA technology.
In this paper, the problems of consortia related to the Japanese semiconductor industry are discussed by focusing on the three consortia concerned with development of semiconductor devices because, both the decline of the Japanese semiconductor industry and the inefficiency of the consortia seem to be caused by the
failure in learning the equipment and material technologies that contribute to the semiconductor industry through semiconductor devices.
MIRAI, SELETE, AND ASPLA
The establishment objectives of MIRAI and Selete are recorded as follows respectively.
If alternatives are not found for materials used in semiconductor Large-Scale Integrated Circuits (LSI), the industry will face a major barrier in raising LSI performance, no matter how many advances are made in fabrication technologies. For example, with materials in use today, thickness reduction will create the problem of increased electricity “leakage” through insulating films, which will increase power consumption. In addition, LSI data-processing signal delay caused by wiring is becoming a major issue facing the industry, raising the demand for the development of new materials that insulate circuit wirings from one another. Further breakthroughs are also being called for in the fields of fine patterning technologies for semiconductors, transistor structures and measuring technologies with extreme resolution.
With an eye to clearing such technological barriers, the seven-year MIRAI project (consisting of a three-year first phase and four-year second phase) comprises R&D in new insulating materials, which will be indispensable for semiconductors of the future, and development of the processing technologies necessary for their practical realization. As a result of these activities, the project will develop and demonstrate the feasibility of semiconductor technologies to markedly improve such basic performance features as the power consumption and data processing speed of LSIs in the 45nm and future technological generations.
Since its establishment of February, 1996, Selete becomes ninth year in this 2004. We are promoting the “ASUKA Project” that is the 5 years project with Semiconductor Technology Academic Research Center (STARC). We advance the joint development of the device and the processing technology for 65nm technological node, and are advancing the early development of the semiconductor high technology by the following themes.
Thus, MIRAI, Selete, and ASPLA target the implementation of semiconductor devices; each has a target technology level classified according to the technology node size, such as MIRAI on 45nm, Selete on 90-65nm, and ASPLA on 90nm. Then, as development tasks to which the three consortia relate mutually, the specific research themes are set, such as “research on elemental
technologies of High-k gate insulating materials, measurement, and analysis” (MIRAI), “research on transistors with new High-k material as gate insulator” (Selete), and “development and improvement of standard processes for 90nm node generation, and management of manufacturing line to verify invested asset and SoC” (ASPLA). MIRAI targets the verification of the applicability of elemental technologies to devices. Selete targets the completion of process modules and ASPLA targets the completion of actual device processes. The design concept for the three projects is that MIRAI investigates materials, Selete introduces them into process modules applicable to mass production, and ASPLA builds experimental devices with them.
Concerning the development of device that uses high dielectric substance material, for instance, the role of MIRAI is a material choice, development of a leading edge process, and that of Selete is the development of the next generation transistor that uses the High-k material. This is confirmed by the following Selete engineers’ comment:
Our processes are not leading edge. The level of the development of top major companies is more advanced than ours. Therefore, the process developed here would not be used by them. However, there is no guarantee that their development will succeed without any problem. If their development fails, our processes will become the substitutions. In addition, the companies in the secondary tier will use our processes.13
However, the differences of the core members of each consortium made it difficult to enable smooth information exchange among MIRAI, Selete, and ASPLA. Though MIRAI and Selete were located in the same building, it was only through open seminars or society meetings that researchers learned of their counterparts’ accomplishments. There was almost no collaboration between the two organizations. This lack of information exchange caused a problem, for example, when MIRAI and Selete independently ran similar research on High-k. Another Selete engineer commented:
The content of our research and the content of the research of MIRAI have consequentially become almost the same. This is because the device structure depends on the material and an appropriate material is selected according to the device structure.14
That is, the development of high-performance transistors is impossible without adequate selection of High-k materials. In reality, evaluation of High-k
material and transistor development should go in parallel. As long as information is not shared between MIRAI and Selete and as long as development themes are separated between MIRAI and Selete, it is inevitable that the two organizations will run similar research projects.
HIGH LEVEL OF KNOWLEDGE INTEGRATION AND COMPLEXITY
Semiconductor devices have the characteristic that the extent of knowledge integrated into them has continuously increased with their functional advance (Fujimura, 2000). In the era up to 16KDRAM in terms of DRAM integration level, we saw little interaction between elemental technologies, only the combination of elemental technologies such as oxidation, etching, and aluminum deposition. Manufacturing equipment was simple and mostly manually operated. Then, in the 64KDRAM era, new process technologies such as RIE, sputtering, and ion implantation emerged, and the equipment became complex.15 A better understanding of the equipment as well as the process phenomena became a requirement to build manufacturing processes. Also, there has been an increase in the number of processes (process modules) for which it is necessary to examine the interactions with adjacent processes, such as film deposition after pre-treatment and aluminum etching followed by ashing.
In the 1M to 4MDRAM era, process establishment became essential for the areas that define device characteristics (functional modules). To solve the stress migration problems, for example, better knowledge of film quality and of the deposition process of underlying inter-metal insulating films or of covering film on aluminum was required to complete the process, in addition to the existing knowledge of aluminum deposition and aluminum etching processes. In the 16M to 64MDRAM era and later, new materials such as copper (Cu) and Low-k came into the limelight. New materials helped to produce new devices like FeRAM and MRAM. We now need to understand material physics as well as process technologies to define device structures. For the design of all transistor equipments and for the choice of High-k material today, High-k materials are selected based on transistor electrical characteristics with the material, and the transistor structure depends on the selected High-k material. Device manufacturers, equip-
ment manufacturers, and material manufacturers cannot each create competitive products without the knowledge of all technology segments.
The copper interconnection process is one of the typical cases that illustrate the interdependence among materials, equipment, and device characteristics. Copper (Cu) is the contaminant that destroys electrical properties of the transistor, so that it is the material that should not be used for integrated circuits. However, the electric resistance of aluminum has become so high for tiny ULSI devices, copper has unavoidably been introduced to semiconductor device manufacturing. Similarly, low-dielectric (low-k) materials have come to be used as the insulator between wiring layers to improve electrical properties of semiconductor devices. Because the dry etching of copper is very difficult, the pattern formation of copper by conventional patterning method using photolithography and dry etching is impossible. Thus, the patterning method called "Damascene" came to be used instead of the dry etching.
The Damascene method of completing the wiring process consists of the following steps: digging up the ditch of the wiring pattern on the insulator; pouring copper to the ditch; and removing the copper overflow from the ditch by CMP treatment of mechanical grinding with a pad like a file. Thus, the insulating material and the low-dielectric substance material that forms the ditch are ground at the same time with copper in CMP. Although copper and the low-dielectric material have different stiffness and fragility, they have to be polished with same speed to form the wiring with enough accuracy. If not, the process afterwards can be hindered by copper protruding beyond the ditch or by buried copper denting.
Thus, the accuracy of the grinding equipment, the physical properties of the low-dielectric substance material, and the device properties relating to the wiring have to be considered when CMP is performed. Creating an accurate copper interconnection using CMP therefore requires the sharing of information among the equipment vendors, the material supplier, and the device manufacturer.
Japanese semiconductor device manufacturers believe that NEC is one year behind Micron Technologies and Motorola of the United States and two years behind Samsung of South Korea late in starting the development of CMP (Chuma and Hashimoto 2007). CMP will also be indispensable to forming the wiring for the semiconductor device in the future. Therefore, the delay in the adoption of this process can have serious competitive consequences. To make up the delay of the Cu wiring technology and to strive for the technological advantage, Japan decided that consortia should focus on R&D in the Cu wiring process, particularly CMP and the low-k materials, and Cu wiring is listed as the R&D theme of MIRAI and Selete. The problem was the need to establish one more consortium—CASMAT—that assumed the Cu wiring technology to be a development theme.
Japanese semiconductor materials manufacturers are playing a major role in the world market and will try to continue to offer high quality and advanced semiconductor materials. But they are now facing the challenge of overcoming the methodology limit of the individual material research to improve the perfor-
mance of the comprehensive set materials under the changing circumstances of rapid progress of nanoscale devices and complex processes. Against this backdrop, it becomes more and more important to have close cooperation between different manufacturers of semiconductor devices, semiconductor materials, and semiconductor equipment in order to promote the concurrent development of processes and materials.
The Consortium for Advanced Semiconductor Materials and Related Technologies (CASMAT) was founded by a group of major Japanese manufacturers of semiconductor materials in March 2003 to help meet this challenge. Its mission is explained on its homepage.
CASMAT is equipped with integrated wafer back-end process by state-of-the-art process equipment which is compatible with 65nm node lithography and 300mm wafer process technology…. The entire process modules are accompanied with various evaluation equipments in order to feed the results back to the material developments.
The stated research task is the
Development of tools that can assist in the comprehensive evaluation of not only the electrical characteristics of semiconductor devices but also their impact on reliability, which we call “integrated component development aid tools,” in addition to the mutual influence between materials, and the same between materials and processes.
Selete is organized only by device manufacturers, and there is no room for the equipment and material manufacturers to participate in its management. However, MIRAI is open to equipment and material manufacturers as well, and eleven equipment and material manufacturers, including Tokyo Electron, ULVAC, and Mitsui Chemicals, have actually joined the consortium. It is no wonder that some companies join both MIRAI and CASMAT. It may actually be rather reasonable to do so since the two consortia have different technology node targets. However, none of the ten equipment or manufacturing companies that are CASMAT members has joined MIRAI.
Though the author is not familiar with the political issues concerning company qualifications to join the consortia, it can be said that the situation must be serious enough. For some reason material manufacturers felt a need to found CASMAT though we already had MIRAI and Selete for the same technology purposes. Whatever the reason is, it means that MIRAI and Selete do not have enough capability to absorb the wisdom of material manufacturers and reflect it in their R&D for improving device performance.
The golden age of the Japanese semiconductor industry from the 1980s into the early 1990s was mainly sustained by DRAM. As DRAM was a commodity product with a common worldwide specification, it was hard to differentiate by
device features and product competitiveness. Reliability and pricing were the sole qualities used in making purchase decisions. In other words, the industry was highly dependent technically on process equipment and/or material. This is why Japanese device manufacturers chose to enclose their technologies by manufacturing the equipment and the materials internally or having them made by related (or subsidiary) companies. Major integrated device makers (IDM) acquired advanced knowledge about all areas of devices, equipment, and material, and then directed the equipment and material manufacturers to give them what they needed. This situation led them to secure better and higher quality equipment and material than was available to U.S. device manufacturers, and their more reliable DRAMs gave them a strong competitive advantage.
Since the late 1990s, however, it has become difficult for device manufacturers to maintain their technological edge in all areas of equipment and material as the technologies advanced, and the enclosure collapsed. When the enclosure collapsed and the advantage in equipment and materials was lost, Japanese device manufacturers could not compete against Korean and Taiwanese device manufacturers who excelled in productivity. Many of the Japanese manufacturers were forced to exit the DRAM business. They tried to strengthen their design capability to differentiate device features, but because U.S. companies were already differentiating device features, Japanese companies could not gain a competitive advantage in these aspects. They could gain a market share only in the digital consumer device market by capitalizing on the strength of digital consumer products made by Japanese manufacturers.
Consortia were established to turn the tide. ASUKA’s predecessor, Phase-1 of Selete, had a mission to evaluate 300mm-compliant equipment. However, it failed to give equipment manufacturers enough feedback information on equipment evaluation results from processing modules they considered necessary for technology development. It could not get cooperation from equipment manufacturers. It dragged the master-servant relationship of the 1980s into the 1990s, so that the consortium did not expect much from the equipment manufacturer and made them produce what was required for their devices. Though some improvement was made in consortia afterward, the device manufacturers still have not yet been able to find an effective strategy to establish cooperation across the industry sectors, and the equipment manufacturers have not escaped their dependencies on device manufacturer leadership. The master-servant relationship still lingers.
Global market share of the Japanese device manufacturers is roughly 27 percent, and the share of the Japanese equipment manufacturers is roughly 30 percent. In contrast, the global market share of the Japanese material manufacturers is about 70 percent, which means material manufactures have the highest competitive power relatively. Under normal circumstances, it should be one of the advantages for domestic device and equipment manufacturers against overseas companies to have strong material manufacturers close at hand. However, it is very much regrettable that they have been unable to have those material manufacturers
participate in Selete or MIRAI, where equipment and material knowledge were expected to be integrated onto devices, and to have left material manufacturers no choice other than to establish their own unique consortium. The Japanese device manufacturers are no longer in a position to educate equipment and material manufacturers but to get support from them.
TOWARD THE INTEGRATION OF VARIOUS TYPES OF KNOWLEDGE
Given that Japanese device, equipment, and material manufacturers could not build an efficient information exchange system, it is not surprising that the device manufacturers did not understand the qualitative changes of the technologies required for the devices. Some ascribe the decline of the Japanese semiconductor industry in the 1990s to equipment and material manufacturers, saying that the advantage in device manufacturing technology was lost because equipment and material manufacturers had exported products that had been refined, using the knowledge and experiences of the device manufacturers.
This is a typical example of the ignorance of technology change. The reason that equipment and material manufacturers sell their products globally is that it is impossible to invest enough in development to fully support the increase of device complexities if their sales are limited to the domestic market. The loss of competitiveness of the device manufacturers should be ascribed to their inability to build a new symbiotic relationship with equipment and material manufacturers suitable for technology advancement.
Even now, device manufacturers have strong concerns about the outflow of expertise through equipment and material manufacturers. It is not easy to maintain confidentiality and exchange information. Consortia should act as a meeting place where each device, equipment, and material manufacturer can improve their unique differentiating technologies through the exchange of these technologies while keeping their secrets.
As was mentioned earlier, there are three consortia today with the mission to bring forth the real devices: MIRAI, Selete, and ASPLA. They were organized so that the functions inherent to IDM were spun off for the purpose of cost reduction. The essence of semiconductor device development is to create a device by consolidating individual process technology. All the device manufacturing companies, including foundries, do such work. In other words, this is the source of differentiation, and achieving 100 percent commonality is only a dream in a free competition society.
In MIRAI, however, companies feel less resistance to information exchange since MIRAI handles next-next generation technologies and beyond, with enough lead time for implementation. Selete or ASPLA, on the other hand, handle next-generation and current-generation technologies, respectively. Therefore, most of the device manufacturers, though participating in Selete and/or ASPLA, run their
own development projects of next-generation processes independently and in parallel. A comment such as “Really necessary and important technology will not be developed by Selete or ASPLA” reflects the attitude that is necessary to refrain from sharing knowledge with each other since the work there might affect their own competitiveness. Those consortia will duplicate their investment for development rather than reduce development cost and consolidate knowledge.
A definition of consortia functions should be based on a thorough consideration of where the arena is, the definition of the technical area where companies share information, and where they compete with each other.
THE CASE OF IMEC IN BELGIUM16
IMEC in Belgium is a successful case in these respects. IMEC does not run R&D on unique processing module technologies except cleaning. Accordingly, they do not develop process equipment, nor do their components include module components such as process chambers. But they do process evaluation and equipment evaluation by functional module unit. They do research on next generation CMOS transistors using the technology, but they do not develop specific devices (e.g., memories and MPUs). But they do research on design technologies. They do not develop specific equipment such as routers using semiconductors, but they do research on wireless communications. IMEC does not do research on or develop the devices, process equipment, and specific equipment, since there are companies who manufacture these products as their main business. They are equipment manufacturers, device manufacturers, and set manufacturers. In other words, the research topics of IMEC are all on industry boundaries, and it works as the bridges that link different sectors.
The member companies of the IMEC can join IMEC’s research projects, get the information, and execute their own unique research projects in the IMEC at the same time. Assume, for example, equipment manufacturer A has developed process equipment that offers advanced processing capability. In the IMEC system, company A can have its private laboratory within the IMEC that excludes other companies, and A can evaluate the equipment with device characteristics by applying the new device as an experiment to CMOS process. At that time, all of the processes, except the one on company A’s equipment, are applied by IMEC personnel to company A’s experimental wafers. So, it is only company A researchers and IMEC personnel who actually see company A’s experimental wafer, and processing of the wafer by the new equipment is carried out by company A’s personnel only. That is, company A can use the pilot line of IMEC to evaluate its equipment while keeping its information confidential. The company can use the results to promote the equipment to device manufacturers. If the device manufacturer is a member of IMEC at the time, it will understand the features of
IMEC CMOS and can accept the evaluation result of company A’s equipment. From a device manufacturer’s viewpoint, this means that the equipment manufacturer obtains the evaluation results of reliable devices, and it saves the device manufacturers from doing the evaluation work from scratch by themselves. That is, they can quickly absorb the equipment and material manufacturer’s wisdom. Similarly, device manufacturers can secure their own lab area in IMEC and develop their unique devices by using the IMEC pilot line.
At IMEC, device, equipment, and material manufacturers can exchange their information while protecting their own differentiating technology secrets through adequate theme selection and organization management. There is no need for device manufacturers to enclose equipment and material manufacturers to assimilate knowledge from them. Instead, they can quickly get the results of development by equipment and material manufacturers.
With increase in the transistor density on a chip, the minimizing pattern size has become smaller and interaction between unit processes has become more complex. To obtain the smaller pattern size with minimizing the undesirable influences of the process interaction, after the era of 1MDRAM, deep understanding of the physical-chemical phenomena in each unit process and the physical-chemical properties of materials has come to be needed. In other words, to develop an effective new process, and to select an appropriate new material, researchers came to have to consider the interactions. In the Japanese consortia newly started, however, it is so difficult for researchers of consortia to get the necessary information for solving the interaction problems because of sectionalized organization. If Japanese chip suppliers want to keep development capability of unit processes with minimum research cost, they need to focus the key process to standardize other processes among the consortia members. A consortium should be established to develop the technologies that agree all members' making them to the standard among members. Before starting the new consortium, members have to characterize the technology.
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Chuma, Hiroyuki, and Norikazu Hashimoto. 2007. "Moore's Law, Increasing Complexity and Limits of Organization: Modern Significance of Japanese DRAM ERA." NISTEP Discussion Paper No. 44. Tokyo, Japan: National Institute of Science and Technology Policy.
Fujimura, Shuzo. 2000. “Handotai Rikkoku Futatabi.” (In Japanese.) Nikkann-Kogyo Shin-bun-sha.
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