DANIEL REED is Vice President for Research and Economic Development at the University of Iowa, where he holds the University Computational Science and Bioinformatics Chair, with joint appointments in Computer Science, Electrical and Computing Engineering and Medicine. Previously, he was Microsoft’s corporate vice president for technology policy. Prior to that, he was Chancellor’s Eminent Professor at the University of North Carolina (UNC) at Chapel Hill, as well as the director of the Renaissance Computing Institute (RENCI) and the Chancellor’s Senior Advisor for Strategy and Innovation for UNC Chapel Hill.
Dr. Reed has served as a member of the U.S. President’s Council of Advisors on Science and Technology (PCAST) and as a member of the President’s Information Technology Advisory Committee (PITAC). As chair of PITAC’s computational science subcommittee, he was lead author of the report Computational Science: Ensuring America’s Competitiveness. On PCAST, he cochaired the Subcommittee on Networking and Information Technology (with George Scalise of the Semiconductor Industry Association) and coauthored a report on the National Coordination Office’s Networking and Information Technology Research and Development (NITRD) Program called Leadership Under Challenge: Information Technology R&D in a Competitive World. In June 2009 he completed two terms of service as chair of the board of directors of the Computing Research Association, which represents the research interests of Ph.D.-granting university departments, industrial research groups and national laboratories.
He was previously head of the Department of Computer Science at the University of Illinois at Urbana-Champaign (UIUC), where the held the Edward William and Jane Marr Gutgsell Professorship. He has also been director of the National Center for Supercomputing Applications (NCSA) at UIUC, where he also led the National Computational Science Alliance, a 50-institution partnership devoted to creating the next generation of computational science tools. He was also one of the principal investigators and chief architect for the National Science Foundation (NSF) TeraGrid. He received his B.S. from Missouri University of Science and Technology and his M.S. and Ph.D. in computer science in 1983 from Purdue University. He is a fellow of the Association for Computing Machinery (ACM), the Institute of Electrical and Electronics Engineers (IEEE), and the American Association for the Advancement of Science (AAAS).
CONG CAO is one of the leading scholars in the study of science, technology, and innovation in China. He is currently an associate professor and reader at the School of Contemporary Chinese Studies, University of Nottingham. Having studied in both China and the United States and in both natural and social science, he received his Ph.D. in sociology from Columbia University in 1997 and has worked at the University of Oregon, the National University of Singapore, and the State University of New York.
Dr. Cao is interested in the social studies of science and technology with a focus on China. He is the author of China’s Scientific Elite (London and New York: RoutledgeCurzon, 2004), a study of the Chinese scientists holding honorific membership in the Chinese Academy of Sciences, and China’s Emerging Technological Edge: Assessing the Role of High-End Talent (with Denis Fred Simon, Cambridge and New York: Cambridge University Press, 2009). His journal
publications have appeared in Science, China Quarterly, Asian Survey, and Minerva, among others.
TAI MING CHEUNG is an associate research scientist at the University of California Institute on Global Conflict and Cooperation (IGCC) located at the University of California, San Diego (UCSD), in La Jolla. He directs the Minerva program on Chinese security and technology, a multiyear academic research and training project funded by the U.S. Defense Department to explore China’s technological potential. His responsibilities include managing the institute’s Track II Program: the Northeast Asia Cooperation Dialogue, which brings together senior foreign ministry and defense officials as well as academics from the United States, China, Japan, South Korea, North Korea, and Russia for informed discussions on regional security issues.
Dr. Cheung is also an associate adjunct professor at UCSD’s Graduate School of International Relations and Pacific Studies (IR/PS), where he teaches courses on Asian security, Chinese security and technology, and Chinese politics.
Dr. Cheung is a long-time analyst of Chinese and East Asian defense and national security affairs, especially defense economic, industrial, and science and technological issues. His latest book, Fortifying China: The Struggle to Build a Modern Defense Economy, was published by Cornell University Press in 2009. The book examines the economic, commercial, and technological foundations of China’s long-term defense modernization that examines the development of the defense industrial complex, the role and prospects for civilian-military integration, and the military dimensions of science and technology policies. He was based in Northeast Asia (Hong Kong, China, and Japan) from the mid-1980s to 2002 covering political, economic, and strategic developments in Greater China and East Asia as a journalist for the Far Eastern Economic Review from 1988–1993 and subsequently as a political and business risk consultant for a number of companies, including PricewaterhouseCoopers. Dr. Cheung received his Ph.D. in war studies from King’s College London in 2007.
JOHN CRAWFORD is an Intel fellow, Digital Enterprise Group, and sets the architectural direction for emerging power and reliability technologies for future Intel processor server platforms. When Crawford joined Intel as a new college graduate in 1977, he worked as a software engineer developing software tools for Intel’s 8086 processor including the code-generation phase of Intel’s Pascal compiler for the 8086. In 1982 he became the chief architect for the Intel386 microprocessor. He was responsible for defining the company’s 32-bit architectural extensions to the already successful 8086/186/286 16-bit product line. In this capacity, he set the architectural direction and later participated in the design of the processor by leading the microprogram development and test program generation. Mr. Crawford made similar contributions as chief architect of the Intel486 processor. He comanaged the design of the Pentium processor from inception through a successful product launch in 1993. Mr. Crawford headed the joint architecture research with Hewlett-Packard that developed the Itanium family architecture, Intel’s 64-bit Enterprise product line. He has been involved with the Itanium family of products since its inception in 1994. In 1995, he received the ACM/IEEE Eckert-Mauchly Award for contributions to computer and digital systems architecture, and in June 1997 he received the IEEE Ernst Weber Engineering Leadership Recognition. Mr Crawford was elected to the National Academy of Engineering in 2002.
Mr. Crawford received a bachelor’s degree in computer science from Brown University in 1975, and a master’s degree in computer science from the University of North Carolina at Chapel Hill in 1977. He holds 23 patents.
DIETER ERNST (senior East-West Center fellow at the full professional level) is an authority on global production networks and research and development (R&D) internationalization in high-tech industries and on industrial and innovation policies in China, the United States and emerging economies, with a focus on standards and intellectual property rights. Earlier positions include senior advisor to the Organization for Economic Cooperation and Development (OECD), Paris; research director of the Berkeley Roundtable on the International Economy (BRIE) at the University of California, Berkeley; and professor of international business at the Copenhagen Business School.
Dr. Ernst has cochaired an advisory committee of the U.S. Social Science Research Council to develop a program on innovation, business institutions and governance in Asia. He has served as scientific advisor to governments, private companies, and international institutions, such as World Bank, the Organization of Economic Cooperation and Development, the UN Conference on Trade and Development and the UN Industrial Development Organization. In the United Sates, Dr. Ernst has served as advisor to the National Science Foundation, Social Science Research Council, U.S.-China Economic and Security Review Commission, Council on Foreign Relations, the National Bureau for
Asian Research, U.S. Department of Commerce, the Deloitte Center for the Edge, and the Frontier Strategy Group.
Relevant publications include Indigenous Innovation and Globalization: The Challenge for China’s Standardization Strategy (2011) [now published in Chinese]; China’s Innovation Policy Is a Wake-Up Call for America (2011); A New Geography of Knowledge in the Electronics Industry? Asia’s Role in Global Innovation Networks (2009); Can Chinese IT Firms Develop Innovative Capabilities within Global Knowledge Networks? (2008); China’s Emerging Industrial Economy-Insights from the IT Industry (with Barry Naughton) (2007); Innovation Offshoring-Asia’s Emerging Role in Global Innovation Networks (2006); “Complexity and Internationalization of Innovation: Why is Chip Design Moving to Asia?", International Journal of Innovation Management, 2005; “Limits to Modularity: Reflections on Recent Developments in Chip Design”, Industry and Innovation, 2005; International Production Networks in Asia: Rivalry or Riches? (2000); and Technological Capabilities and Export Success: Lessons from East Asia (1998).
MARK D. HILL is a professor of computer science and electrical and computer engineering at the University of Wisconsin–Madison. Dr. Hill’s research targets computer design and evaluation. He has made contributions to parallel computer system design (e.g., memory-consistency models and cache coherence), memory-system design (caches and translation buffers), computer simulation (parallel systems and memory systems), software (e.g., page tables and cache-conscious optimizations for databases and pointer-based codes), and transactional memory. For example, he is the inventor of the widely used 3C model of cache behavior (compulsory, capacity, and conflict misses).
Dr. Hill’s current research is mostly part of the Wisconsin Multifacet Project that seeks to improve the multiprocessor servers that form the computational infrastructure for Internet Web servers, databases, and other demanding applications. The Multifacet work focuses on using the transistor bounty provided by Moore’s Law to improve multiprocessor performance, cost, and fault tolerance, while also making these systems easier to design and program.
Dr. Hill was named an ACM fellow (2004) for contributions to memory consistency models and memory system design, elevated to a fellow of the IEEE (2000) for contributions to cache memory design and analysis, and was awarded the ACM SIGARCH Distinguished Service Award in 2009. He has won three important University of Wisconsin awards: Kellett Mid-Career in 2010, Vilas Associate in 2006, and Romnes Faculty Fellowship in 1997. He co-edited Readings in Computer Architecture in 2000, is coinventor of more than 30 U.S. patents (several of which have been coissued in the European Union and Japan), was an ACM SIGARCH director (1993–2007), and won a National Science Foundation Presidential Young Investigator award in 1989. He is coauthor of five papers selected by IEEE Micro Top Picks and co-won the best paper award at the International Conference on Very Large Databases (VLDB) in 2001. He has held visiting positions at Advanced Micro Devices (2011), University of Washington (2011), Columbia University (2010), Polytechnic University of Catalonia (2002–2003) and Sun Microsystems (1995–1996). Dr. Hill earned a Ph.D. in computer science from the University of California, Berkeley, in 1987, an M.S. in computer science from UC Berkeley in 1983, and a B.S.E. in computer engineering from the University of Michigan–Ann Arbor in 1981.
STEPHEN W. KECKLER is the senior director of architecture research at NVIDIA and professor of both computer science and electrical and computer engineering at the University of Texas (UT) at Austin, where he has served on the faculty since 1998. His research interests include parallel computer architecture, technology-scalable architectures, very-large-scale integration (VLSI) design, high-performance computing, energy-efficient computing, and on-chip interconnection networks. He has developed both commercial chips at Intel and parallel computing prototype chips at MIT and UT Austin. At MIT, he was the principal architect of the M-Machine multicomputer, a research machine that was one of the first multicore processors and included extremely efficient inter-thread communication and synchronization mechanisms. His research team at UT Austin developed scalable parallel processor and memory system architectures, including nonuniform cache architectures; explicit data graph execution processors, which merge dataflow execution with sequential memory semantics; and micro-interconnection networks to implement distributed processor protocols. His research team at NVIDIA is developing extreme energy-efficient computing technologies for massively parallel chips and systems.
Dr. Keckler was named fellow of the ACM (2011) for contributions to computer architectures and technology modeling, and was elevated to a fellow of the IEEE for contributions to computer architectures and memory systems. He received the 2003 ACM Grace Murray Hopper Award for ground-breaking analysis of technology scaling for high-performance processors that sheds new light on the methods required to maintain
performance improvement trends in computer architecture, and on the design implications for future high-performance processors and systems. He won an NSF CAREER award (2000), was selected as an Alfred P. Sloan research fellow (2002), won the Edith and Peter O’Donnell Award for Engineering (2010), and won six IBM Faculty Partnership awards. Dr. Keckler is coauthor of four papers selected by IEEE Micro Top Picks and co-won best paper awards at the 2009 International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS) and the 2011 International Symposium on Performance Analysis of Systems and Software (ISPASS). He has also won top teaching awards at the University of Texas at Austin, including the College of Natural Sciences Teaching Excellence Award (2001) and the President’s Associates Teaching Excellence Award (2007). Dr. Keckler also served as a member of the Defense Science Study Group, sponsored by the Defense Advanced Research Projects Agency (DARPA), (2008–2009). Dr. Keckler earned a B.S. in electrical engineering from Stanford University (1990), and an M.S. (1992) and a Ph.D. (1998) in computer science from the Massachusetts Institute of Technology.
DAVID LIDDLE has been a partner at U.S. Venture Partners, a Silicon Valley–based venture capital firm, since 2000. He cofounded, and between 1992 and 1999, he served as president and CEO of, Interval Research Corporation, a Silicon Valley–based laboratory and incubator for new businesses focusing on broadband, consumer devices, interaction design, and advanced technologies. Prior to cofounding Interval with Paul Allen, Dr. Liddle founded Metaphor, which was acquired by IBM in 1991, which named him vice president of business development for IBM Personal Systems. Dr. Liddle’s extensive experience in research and development has focused largely on human-computer interactions and includes 10 years at Xerox Palo Alto Research Center (PARC), from 1972 to 1982. He has been a director of Sybase, Broderbund Software, Borland International, and Ticketmaster, and is currently on the board of the New York Times Company. His board involvement at U.S. Venture Partners includes Electric Cloud, Instantis, Klocwork, MaxLinear, and Optichron. Dr. Liddle has served on the DARPA Information Science and Technology Committee, and as chair of the National Academy of Sciences Computer Science and Telecommunications Board.
Dr. Liddle earned a B.S. in electrical engineering at the University of Michigan and a Ph.D. in electrical and engineering and computer science at the University of Toledo, where his dissertation focused on reconfigurable computing machines and theories of encryption, encoding, and signal recovery. His contributions to human-computer interaction design earned him the distinction of senior fellow at the Royal College of Art.
KATHRYN MCKINLEY is principal researcher at Microsoft Research and holds an Endowed Professorship of Computer Science at the University of Texas at Austin. She previously was a professor at the University of Massachusetts, Amherst.
Dr. McKinley’s research interests include programming language implementation, compilers, memory management, runtime systems, security, reliability, and architecture. Her research group has produced numerous tools, algorithms, and methodologies that are in wide research and industrial use, such as the DaCapo Java Benchmarks, the TRIPS compiler, the Hoard memory manager, the Memory Management Toolkit (MMTk), and the Immix mark-region garbage collector. For example, the Apple operating system uses the Hoard memory management algorithm, the TRIPS compiler was the first demonstration of a compiling general-purpose programming language to execute on a dataflow architecture, and the DaCapo Benchmarks are the most widely used Java benchmarks for performance and verification in both research and testing.
Dr. McKinley was named an ACM fellow (2008) for contributions to compilers and memory management and an IEEE fellow (2011) for contributions to compiler technologies. She was awarded the 2011 ACM SIGPLAN Distinguished Service Award. She has served as the technical program chair for ASPLOS, PACT, PLDI, ISMM, and CGO (ACM and IEEE conferences). She was coeditor-in-chief of ACM’s Transactions on Programming Language Systems (or TOPLAS) (2007–2010). She was a Computer Research Association’s Committee on the Status of Women in Computer Science (CRA-W) board member (2009–2011) and is currently a cochair of CRA-W (2011–present), which seeks to improve the participation of women in computing research nationwide. Her research awards include two CACM Research Highlights Invited Papers (2012, 2008), IEEE Micro Top Picks (2012), Best Paper at ASPLOS (2009), David Bruton Jr. Centennial Fellowship (2005–2006), six IBM Faculty Fellowship Awards (2003–2008), and an NSF CAREER Award (1996–2000). She is a recipient of the 2011 ACM SIGPLAN Software Award. Dr. McKinley has graduated fourteen Ph.D. students. She received a B.A., M.S., and Ph.D. from Rice University.