Skip to main content

The Future of Supercomputing An Interim Report (2003) / Chapter Skim
Currently Skimming:

2. Supercomputing Past and Present
Pages 9-17

The Chapter Skim interface presents what we've algorithmically identified as the most significant single chunk of text within every page in the chapter.
Select key terms on the right to highlight them within pages of the chapter.


From page 9...
... commissioned the NSF Blue Ribbon Panel on High Performance Computing to investigate the future changes in the overall scientific environment due to rapid advances in computers and scientific computing.2 The panel's report, From Desktop to Teraflop: Exploiting the U.S. Lead in High Performance Computing (the Branscomb report)
Read the entire page →
From page 10...
... The recommendation of the task force was to continue to maintain a strong Advanced Scientific Computing Centers program. Congress asked the National Research Council's Computer Science and Telecommunications Board to examine the High Performance Computing and Communications Initiative (HPCCI)
Read the entire page →
From page 11...
... The Department of Defense sponsored the Report of the Defense Science Board Task Force on DOD .~unercomnutin~ Need.v ~3 The task force found that there is a significant need for hi~h-nertc~rmance -- I -- -- -- -r -- -- -- o - -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- I -- -- -- -- -- - -- -- -- -- - -- -I -- r-computers that provide extremely fast access to very large global memories and that such computers support a crucial national cryptanalysts capability. Task force recommendations included providing additional financial support for the development of the Cray SV-2 (now the X1)
Read the entire page →
From page 12...
... The engineering and prototype development element will build operational prototypes and system level testbeds. The report also emphasizes the importance of high-end computing laboratories that will test system software on dedicated large-scale platforms; support the development of software tools and algorithms; develop and advance benchmarking, modeling, and simulations for system architectures; and conduct detailed technical requirements analysis.
Read the entire page →
From page 13...
... Architecture Contemporary supercomputers are all built by clustering large numbers of compute nodes. They span a spectrum of architectural choices, from clusters that are assembled from low-cost, high-volume components, to systems that are custom built for high-end scientific computing.
Read the entire page →
From page 14...
... A custom memory-connected interface, typically proprietary, can be used to increase bandwidth, reduce latency, or provide added functionality. Such interfaces are usually paired with higherperformance custom switches.20 In particular, a custom interface can directly support shared memory communication, allowing a processor to access the memory of a remote node via load and store i9Temporal locality is the property that data accessed recently in the past are likely to be accessed soon in the future.
Read the entire page →
From page 15...
... ASCI White system, use Power SMP nodes connected with an IBM proprietary switch using a proprietary interface (Power 4 systems currently use a standard I/O interface) ; global communication uses message passing.
Read the entire page →
From page 16...
... The availability of a large number of vector registers and of vector load instructions makes it possible to prefetch data and to hide memory latency for codes where data accesses are predictable but not spatially localized. Codes that vectorize well can achieve a high fraction of the peak floating performance of the SX-6.
Read the entire page →
From page 17...
... The primary challenge introduced by supercomputing is that many conventional algorithms for these problems must be modified so as to scale effectively to much larger data sets or numbers of processors and to run efficiently on machines with deep memory hierarchies. For example, a numerical simulation on a very large mesh may involve converting an algorithm from one using dense matrices or even direct solvers on sparse matrices to one using a specialized iterative method that may still use a parallelized direct method on subproblems.
Read the entire page →

Key Terms

  • scientific computing
  • shared memory
  • message passing
  • supercomputer centers
  • proprietary switch

  • memory bandwidth
  • nodes connected
  • smp nodes
  • security community
  • vector supercomputers

  • strategic computing
  • centers program
  • parallel programming
  • computing initiative
  • computational science

  • memory references
  • environment available
  • vector processors
  • communications initiative
  • switch interfaces

  • development element
  • memory communication
  • agencies addressing
  • computing act
  • programming environment

  • commodity hpcs
  • hide memory
  • ribbon panel
  • global bandwidth
  • lax report


    • This material may be derived from roughly machine-read images, and so is provided only to facilitate research.
    More information on Chapter Skim is available.