Materials for High-Density Electronic Packaging and Interconnection (1990) / Chapter Skim
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2 MICROELECTRONIC SYSTEM TRENDS AND PACKAGING NEEDS
2 MICROELECTRONIC SYSTEM TRENDS AND PACKAGING NEEDS
Pages 21-40
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From page 21... ...
several chips; For ~ -important: _ · die attachment chip pinout pinout conf figuration heat removal signal rise time power lead inductance power supply current interline coupl ing , that deal with interfacing c lips are covered, as are those that deal with interconnecting the terms first-level and second-level packaging are not used. interlacing to a single chip, the following additional requirements are those requirements protection from the environment 21
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From page 22... ...
The requirements listed above are qualified, where possible, for each of the system types. S CALING THEORY Scaling theory Is important in understanding the driving forces that affect the trends of integrated circuit chips.
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From page 23... ...
The minimum feature size that optical lithography is capable of producing is limited by the wavelength of light used, and it therefore has a very fundamental limitation. Electron beam lithography can provide very small feature sizes with the use of proper photoresist material.
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From page 24... ...
Impurity concentration Wiring current density Gate delay 1/x · 1 · 1/a · 2 ~ ·O 1/ ~ · 1/~ Powe r /gate ~ 3 · 1/~2 Source: Based on Baccarani et al., 1984; Dennard, 1986 When the power supply voltage is held fixed, then ~ = ke, where k is a proportional ity cons tent , and the gate delay scaling factor becomes k/~2. There are limits to how far generalized scaling can be extended, since, as increases, gate-to-insulator failure increases and hot-carrier mechanisms produce long-term degradation.
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From page 25... ...
In this experiment, the power supply voltage was scaled by about a factor of 2, from 2.5 to 1.2 volts, so as to keep the electric field in the device constant. These scaled NMOS NOR circuits were patterned with a vector-scan electron beam exposure system having a capability of producing 0.5 Em features with a standard deviation of +0.05 Em in both feature size and level-to-level overlay.
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From page 26... ...
applied general scaling theory to a 0.25 Em NMOS FET and calculated that a device with a fan-out of 3 would have a gate delay of about 200 psec, with a power dissipation of 50 low at a power supply voltage of 1.0 volt. In relating their results to CMOS, they state, "Due to the lower hole mobility, and to the larger sheet resistance of pa shallow junctions, however, quantitatively different results are obtained in this case, leading to somewhat modified design tradeoffs." They are saying that the design of the e-channel PET in the CMOS circuit must be optimized differently than the p-channel PET.
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From page 27... ...
. Experimental evidence has overwhelmingly shown that polysilicon emitter contacts make it possible to vertically scale bipolar transistors and improve circuit performance without unacceptable degradation in current gain.
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From page 28... ...
Logic gate delays in these ultrafast chips of as little as 10 to 100 psec make it possible to design signal processors that are already achieving clock rates as great as 2 GHz. Furthermore, gallium arsenide (GaAs)
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From page 29... ...
Rent's rule is used here to predict the pinout of future integrated circuits and the interchip wiring complexity of highly parallel computer architectures of the future. Two empirical constants, ~ and a, appear in Rent's rule.
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From page 30... ...
Human understanding is more likely to occur when the subsystems do not have complex interactions but instead interface with minimal information interchange. It appears that the following values of constants appear to characterize different types of chips and systems: · Memory chips, ~ - 6, ~ ~ 0.12 Functionally partitioned chips, ~ ~ 10, ~ ~ 0.2 Modules and boards, ~ z 82, ~ ~ 0.25 · Highly partitioned chips, ~ = 2, ~ ~ 0.5
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From page 31... ...
As a result, a natural evolution from one gate array to the next, keeping design style and design tools similar, will necessarily scale the pinout as the square root of the number of gates. Thus, the pinout of highly partitioned chips may in fact be limited more by the interconnect technology available than by the inherent needs of the logic, and therefore, in designing packages for the future, perhaps higher exponents might be appropriate.
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From page 32... ...
Consider the problem of providing pins for integrated circuits, which are planar (two-dimensional)
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From page 33... ...
0.4 0.07 0.17 DC power supply current (A) 6.7 33 10 Environmental protection Essential Essential Essential Chip Interconnection Packaging If the signal propagation delay from chip to chip and the signal rise time for interchip communication at least match the inter-latch delay for the chips, then signals can be transmitted from one chip to another during a single clock cycle, and the packaging will not substantially degrade system performance.
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From page 34... ...
This works well only for limited chip pinout and limited board pinout. It works best for chips with perimeter bonding, or whose first-level packaging provides perimeter connections, because of the difficulty of using essentially a two-dimensional scheme to connect to a two-dimensional pinout array, given the normal wire size, spacing needed to reduce crosstalk and adj acent- conductor shorts, and the pad or connector size .
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From page 35... ...
In the case of the thermal conduction modules, the horizontal spacing between wires in one plane is 5 mils, the distance between planes is 10 mils, or 20 mils if a ground plane lies between for shielding, and ache pitch of vies is 25 mils. In contradistinction to the moderate clock rate described throughout this report, packaging intended for the fastest clock rate devices (both silicon and GaAs)
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From page 36... ...
~ SOME PACKAGE DES IGN CONS IDERATIONS The single - chip and multichip modules are described irk this section to point out the techniques used to handle the interconnects and the problems encountered in each type. Single-Chip Modules Single-chip modules (SCMs)
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From page 37... ...
The mismatch in thermal expansion coefficient between the MCM substrate material and the chip material is aggravated when the distance between the extreme farthest connections to the chip increases. Since there are 600 such connections, there will be an array of connections with about 25 connections on a side.
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From page 38... ...
1984. Generalized scaling theory and its application to 1/4 micrometer MOSFET Design.
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From page 39... ...
1987. Experimental technique for characterizing of IEEE International Electron Device Meeting, Technical Digest, pp.
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