Materials for High-Density Electronic Packaging and Interconnection (1990) / Chapter Skim
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3 PACKAGING STRATEGIES AND ASSOCIATED MATERIALS AND PROCESS REQUIREMENTS
3 PACKAGING STRATEGIES AND ASSOCIATED MATERIALS AND PROCESS REQUIREMENTS
Pages 41-58
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From page 41... ...
In the PWB approach , s ingle - chip modules (SCMs) , the first packaging level, are assembled on a printed wiring board, the second packaging level, as individual packages by either through-hole or surface mounting using soft solder joints.
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From page 42... ...
If a surfacemounted package has more than 256 pins, then, because of the maximum permitted wiring density of 40 lines per inch, the innermost PTHs underneath the package can no longer be reached, and at least some package pins must be routed to PTHs outside the package outline. This is true for square package outlines.
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From page 43... ...
Since even 2 or 3 VLSI chips together can exceed this number of I/Os, a significant number of chips can be interconnected on the PWB only if the pinto-gate ratio can be drastically reduced, normally well below that predicted by Rent's rule. For example, for an array processor design using a mix of 100 VLSI logic and memory chips for a total of 4.36 million gates, the designer is presented with 8600 signal I/O and power and ground pins on the chip level.
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From page 44... ...
In addition, the substrate is not subj ect to conventional PWB design rules and assembly restrictions. Multichip-module technologies can be grouped roughly into thick-film multichip modules using ceramic dielectrics and thin-film modules using polymeric dielectrics.
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From page 45... ...
The thick-film multilayer approach has found its most significant application in linear circuits where thick-film resistor functional-trimming requirements make this approach cost-efficient. The second thick-film, multichip approach currently in use employs a cofired ceramic multilayer substrate that contains multiple conductor and dielectric levels fused into a three-dimensional block.
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From page 46... ...
Thin-Film Multichip Modules Using Polymeric Dielectrics The new packaging approaches now emerging, intended to increase the packing density to well above 25 percent, all attempt to employ processes analogous to those used in the processing of the VLSI chips themselves. In particular, the interconnecting conductor pattern is deposited by thin-film deposition techniques that are amenable to photolithographic definition and etching to achieve much higher wirability than was possible for the thickfilm approach.
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From page 47... ...
SB PGA Low attach Heat removal 10,5,20 inductance/ TCE match Silicon Aluminum Polyimide WB WB Vendor/TCE match 40,5,100 Alumina Copper Polyimide Overlay WB No masks/fast Must remove 25,5,75 prototype/low overlay to attach inductance replace chips Silicon Various VariousBeveled Various Handle high pin Beveling step chip edge count/TCE match limited line routing MCC8 Alumina Copper Polyimide TB TB Programmable Silicon 15,6,50 interconnect HP9 Ceramic Copper Polyimide Augat10 Copper Copper Polyimide l (Rogers) Steel 100,25,250 1 NTTll Ceramic Copper Polyimide ~ No detailed data available 25,6,50 NTK12 Ceramic Multiple Polyimide ~ 25,5,65 J Mitsubishi13 Ceramic Copper Polyimide 50,5,100 References listed separately at end of table *
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From page 48... ...
Yasuda, S Yamaguchi, and Taichi Kon, "A Fine-Line Multilayer Substrate with Photo-Sensitive Polyimide Dielectric and Electroless Copper Plated Conductors," Proceedings of the 3rd IEEE/CHMT International Electronics Manufacturing Technology Symposium, pp.
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From page 49... ...
The interconnect issues, which all of these high-density approaches using bare chips must face, are listed in below. In many cases, line-density demands conflict with requirements on crosstalk, yield, ease of fabrication, ease of repair and circuit changes, and cooling difficulty.
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From page 50... ...
in having more functions integrated on the same monolithic piece of silicon, much larger than a VLSI chip and normally of full wafer size. The attractiveness of WSI is in its promise of greatly reduced cost, high performance, higher level of integration, greatly increased reliability, and significant application potential.
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From page 51... ...
PACKAGING MATERIALS REQUIREMENTS The required packaging improvements on all packaging levels are summarized in Tables 3-2 through 3-5 in the light of the VLSI chip technologies expected to be available in the future, as well as the future systems requirements. The latter include performance, electrical noise control, packaging density, reliability, and manufacturability.
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From page 52... ...
operas i on Lower ~ dielectric, low p conductors Multi layer s ~ gna l l ines E lectrical Noise Control Density __ Reliability Manufacturability Cross wafer communication, More functions per cm2 TCE compatibility Fault and failure d i st r i bused to substrate, to l erance power supplies keep small and matched Packag i ng Dens Sty Ground planes on wafers, impedance contra l H i gh ~ decaps on wafers, distributed power supp l i es on wafer Superconduct i ng connect i ons No heat spreading on wafer 1.~-V power Low IR in Tight control Distributed power supplies power leads of L, C, R supplies on wafer, high ef f i c i ency, power by light 3-D construction Other EMI sens i t i v i ty = not applicable or data not available Shielded connector Damage contra 1 i n repair; fault isolation, on-chip repair and rewiring, easy chip and wafer rep lacement Bu l letproof Low-res i stance passivation joints for direct .
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From page 53... ...
low Rid TCE compatibility Void control and inspectof die and substrate, ability of die attach fatigue 100-psec rise High ~Distributed - Demountable 3-D and settling conductors, power construction times low ~supplies (tight spacing) dielectrics, optical fibers 1000 I/Os 1 mil pitch, Staked vies Staked vies TCE compatibility Damage control in repair; 1:1 aspect solder control, outer ratio lead bonding materials for TAB, engineering change pad periphery, planarizability 256 - High ~ decaps High ~ decaps simultaneously closely switching I/Os located near chip High power Low IR drops - No heat If liquid cooling: density in signal and spreading corrosion, power lines possible charge transport 1.5-V power Low forward Tight R
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From page 54... ...
High efficiency power supplies, power by light Low IR drops ln power supplies T i ght board-to -boa rd spac 1 ngs - EM I, EMP red i at i on upset Manufacturabi 1 Sty TCE compati b i 1 i ty of package to board, fat i Due, barrel cracking If 1 iquid cool ing: corrosion, board stability, charge transport Corrosivity of Cu board coatings. deterioration in sliding contact surface Demountable 3-D construction Solder control, damage control in repair, engineering change pad periphery, 10-mil lead pitch, lead fragility and control, lead solderability = not applicable or data not available
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From page 55... ...
. _ Performance Electrical Noise Control Optical fibers Impedance control Packaging Density __ Blind vies Lateral thermal conductivity, highefficiency heat exchangers, plumbing, radiators Reliability Manufacturabil Sty TCE compatibility board to connectors, fatigue Reliable Remountable Tighter con contacts nector pitch, 3-D construc tions, de mountability If liquid cooling: -corrosion, -compatibility, -charge transport.
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From page 56... ...
56 SUMMARY OF FUTURE PACKAGING MATERIALS AND PROCESSES NEEDS Future packaging needs are summarized below and include the following: ~ Fusible link materials with reversibility; · Materials for fuses and antifuses; · Multilevel interconnection processes on silicon; · Thin and thick film magnetic materials for compact power supplies; Low-resistance contacts; Compatible power-device and digital-device processing; lIinority-carrier quality GaAs on silicon substrates; Inr~er lead capability down to a 2-mil pitch; High-yield, high-reliability metallurgical microjoining techniques; "Bullet-proof" chip coatings of "hermetic" quality; Corrosion resistance of chip and package materials toward liquid coolants |
From page 57... ...
57 · Inspectable joint materials; · Fine lead control; Quantum jump in connector reliability; Connectors with lead pitches down to 10 mils; "Smart" connectors and mixed optical and electrical connectors . Packages with windows transparent in certain wavelength ranges; · Method of coupling to incoming light beams ; · Shield conductors in Z-direction; J Laser processes for multilayer fabrication, · Benign repair proces ses ; and Low- loss dielec~cri cs at high frequencies Greater than 1 GHz
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